Objective
The proposed new, dense stack will be obtained as follows :
The chips are thinned down to 5-10 µm and then, using planarization techniques as used in semiconductor processing, the 3D stack is formed on a silicon substrate by depositing layers of dielectric onto which a metallization pattern is formed. The thinned chips are placed on top of each dielectric layer and the vertical interconnection is achieved with metallized vias. The final stack has a thickness comparable to that of standard silicon chips.
Therefore UTCS results in a multichip miniaturisation having the same physical dimensions as monolithic integration without the drawbacks.
UTCS will deliver a new, very dense, 3D stacking technology for semiconductor chips. This very dense, ultra-thin stacking technology is of interest to all electronics industries where size and weight are important for product acceptance. These include all portable applications like telecom terminals, PDAs, portable computers, medical implant, etc., and aerospace where both in satellites and in avionics weight and size are major parameters.
Another advantage for industry is the possibility of using standard chips from different vendors, therefore applicable in the short term without the need of expensive re-designs.
Fields of science (EuroSciVoc)
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques.
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques.
- engineering and technologymechanical engineeringvehicle engineeringaerospace engineeringsatellite technology
- natural sciencesphysical scienceselectromagnetism and electronicssemiconductivity
- natural scienceschemical sciencesinorganic chemistrymetalloids
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Call for proposal
Data not availableFunding Scheme
CSC - Cost-sharing contractsCoordinator
92000 Nanterre
France