Final Report Summary - HSDAC (A 16-bit, 2 Giga -sample-per-second, Digital-to-Analog Converter with 85 dB SFDR at Fout=400MHz.)
High resolution high speed digital to analog converters (DACs) that offer low distortion are among the most important integrated circuits utilized in Universal Mobile Telecommunication Systems (UMTS) and Long Term Evolution (LTE) basestations and Data Over Cable Interface Specification (DOCSIS) compliant digital TV broadcasting. There is ongoing demand to generate spectrally pure waveforms at higher output frequencies, using advanced DAC design techniques.
Spurious free dynamic range (SFDR) is generally used as the metric to optimize DAC distortion performance. DAC SFDR is usually dominated by third harmonic distortion (HD3), which causes third order intermodulation distortion (IMD3), which in turn deteriorate the adjacent carrier leakage ratio (ACLR) of communication systems, causing increased bit error rates (BER).
The HSDAC project is a major attempt to reduce DAC SFDR at higher output frequencies. The industry’s state of the art in DAC SFDR was 67 dB at 200 MHz output frequency as of 2013, and that benchmark is raised by the industry to 74 dB at 400 MHz in 2014. HSDAC project’s proposed target SFDR is 85 dB, which is 9 dB above the best available DAC as of 2014.
A 180 nm, 3.3V 16-bit 1.28 Msps CMOS dual DAC, which uses a conventional PMOS double cascode current source architecture is designed, laid out and simulated using parasitic extraction, corners and monte carlo analyses. Even after very careful optimization of transistor sizes, this DAC could not exceed 78 dB SFDR at 240 MHz with 0.5V p-p differential output swing. To achieve 78 dB result, switch sizes are minimized, current sources are trimmed, clock and AVDD networks had to be distributed using tree structures, and common centroid techniques are used to reduce segment to segment timing delays. This conventional architecture is then pushed to the second Nyquist zone using return to zero (RZ) resetting, to generate 1.1 GHz output frequency. 85 dB SFDR was achieved at a low output swing, after introducing clock tree timing trimming under digital control. Without timing trim, SFDR dropped to 80 dB. A double data rate (DDR) LVDS intefarce and a digital filter with quantization properties to support 95+ dB SFDR are also designed, laid out and simulated to support this DAC.
A second DAC, which uses a folded cascode, continously on current steering cell architecture is designed, laid out and simulated. This architecture beat all specifications at schematic level with over 90 dB SFDR, after current source and clock timing trim; however, high performance layout proved extremely difficult. A first approach to layout optimized size, but digital cross-talk to NMOS folded cascode stack became a bottleneck for SFDR. In a second approach to layout, DAC size and the timing delays had to increase to avoid digital cross-talk. Further layout iterations are ongoing to exceed 85 dB SFDR in post layout simulation.
The host institute, Istanbul Technical University received a new DAC research grant from Turkish Scientific and Technological Council TUBITAK, as a result of the progress made in the HSDAC project. The HSDAC Project already generated multiple publications and master's theses, and additional publications are in preparation.
Spurious free dynamic range (SFDR) is generally used as the metric to optimize DAC distortion performance. DAC SFDR is usually dominated by third harmonic distortion (HD3), which causes third order intermodulation distortion (IMD3), which in turn deteriorate the adjacent carrier leakage ratio (ACLR) of communication systems, causing increased bit error rates (BER).
The HSDAC project is a major attempt to reduce DAC SFDR at higher output frequencies. The industry’s state of the art in DAC SFDR was 67 dB at 200 MHz output frequency as of 2013, and that benchmark is raised by the industry to 74 dB at 400 MHz in 2014. HSDAC project’s proposed target SFDR is 85 dB, which is 9 dB above the best available DAC as of 2014.
A 180 nm, 3.3V 16-bit 1.28 Msps CMOS dual DAC, which uses a conventional PMOS double cascode current source architecture is designed, laid out and simulated using parasitic extraction, corners and monte carlo analyses. Even after very careful optimization of transistor sizes, this DAC could not exceed 78 dB SFDR at 240 MHz with 0.5V p-p differential output swing. To achieve 78 dB result, switch sizes are minimized, current sources are trimmed, clock and AVDD networks had to be distributed using tree structures, and common centroid techniques are used to reduce segment to segment timing delays. This conventional architecture is then pushed to the second Nyquist zone using return to zero (RZ) resetting, to generate 1.1 GHz output frequency. 85 dB SFDR was achieved at a low output swing, after introducing clock tree timing trimming under digital control. Without timing trim, SFDR dropped to 80 dB. A double data rate (DDR) LVDS intefarce and a digital filter with quantization properties to support 95+ dB SFDR are also designed, laid out and simulated to support this DAC.
A second DAC, which uses a folded cascode, continously on current steering cell architecture is designed, laid out and simulated. This architecture beat all specifications at schematic level with over 90 dB SFDR, after current source and clock timing trim; however, high performance layout proved extremely difficult. A first approach to layout optimized size, but digital cross-talk to NMOS folded cascode stack became a bottleneck for SFDR. In a second approach to layout, DAC size and the timing delays had to increase to avoid digital cross-talk. Further layout iterations are ongoing to exceed 85 dB SFDR in post layout simulation.
The host institute, Istanbul Technical University received a new DAC research grant from Turkish Scientific and Technological Council TUBITAK, as a result of the progress made in the HSDAC project. The HSDAC Project already generated multiple publications and master's theses, and additional publications are in preparation.