Ultra Low Energy Vertically Integrated Circuits

Final Report Summary - ULEVIS (Ultra Low Energy Vertically Integrated Circuits)

The current integrated circuit scaling, or as it is popularly known “Moore’s Law” hits two major roadblocks or walls in the 21st century. One wall is the atomic level feature sizes of the current devices forcing the capabilities of even nano-scale implementations. The other wall is the total power consumed per unit area exceeding the capabilities thermal dissipation techniques limiting the maximum device densities. The solution to the feature size problem is scaling in the orthogonal direction to the conventional device plane - the 3D integration. Between the feature size and power dissipation issues, the real roadblock going forward is the power consumption. Since most of the thermal management solutions require also added power, the total power consumed by such a system increases further.

The solution to the power problem is the use of ultra-low power design approaches. Our solution is a unique combination of ultra-low power design approaches with 3D integration of the processor and memory to provide an optimal performance to the user. The use of low power (energy) eliminates the thermal dissipation problem of the 3D integration whereas 3D integration enables dense device integration in small volumes to solve the space-time trade-off in ultra-low power design approaches. The result will be a vertically integrated circuit with power efficiencies several hundred times better than current dedicated processors.
The sweet spot was found to be about 90-130 nm technology nodes where one order of the magnitude reduction was achieved without major delay penalty at the inverter level.. This study demonstrated that there is a critical need to have a low-temperature design approach at device layer to benefit from 3D integration. Otherwise, the negative effects of the increased temperature, eliminates the miniaturization advantage of 3D integration. The study further highlighted a new field of application in the neuromorphic computing as highlighted in the next section.
The interactions with European researchers during this work allowed our team to join one of the winning FET-Flagship programs, the “Human Brain Project” where they need an electronic system to produce a performance like a “brain” with only few 10s of watts. The exposure gained during this project further allowed our team to be invited to several ongoing project proposals in Europe: FITNESS: (Full Integrated Transceiver for Next generation Emergency ServiceS), GREETINGS: (GREEn compuTING) and PANACHE: (Pilot line for Advanced Nonvolatile memory technologies for Automotive microControllers, High security applications and general Electronics) where low power integration techniques are needed.
Frost & Sullivan includes 3D integration in its latest Global Top 10 Hot Technologies to Invest especially in target market segments including CMOS image sensors (CIS), memory, processors, and FPGAs . Research by an European market intelligence company, Yole Development, shows that despite a worldwide economic recession, the R&D activity linked to 3D companies has reached “unprecedented levels”. Jeff Perkins, general manager of Yole, predicts that 3D TSV technologies will be one of an assortment of offerings by 2015.

Final Report Summary - ULEVIS (Ultra Low Energy Vertically Integrated Circuits)

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