Final Report Summary - MNT EUROPE (Staircase towards European MNT infrastructure integration)
The MNT EUROPE project was defined to integrate Micro- and nano-technology (MNT) research capabilities in Europe into the form of a distributed platform for Research and development (R&D). With this aim in view, different networking and joint research activities have been defined to achieve a strategic alliance between the five major European microelectronics and MNT research centres and the creation of a common technology portfolio.
Organisational and strategic agreements, exchange of people and of knowledge have been undertaken in order to converge towards a definition of common roadmaps. This was the aim of the three networking activities of the project:
1.'Creation of the environment and legal framework to allow the integration of activities' to significantly lower the barriers to collaboration between the participant organisations in particular legal issues and those related to the lack of personal relationships.
2.'Preparing the integration' which focuses on building a common view on the future developments;
3.'Scheduling the exploitation' which organises the operational phase of the alliance: global management, external collaboration, dissemination of the alliance concept.
In parallel, and in order to enhance the alliance platform capabilities and to encourage the interoperability by the creation of a common technology portfolio, three joint research activities have be undertaken, aiming to develop new added functionalities to Integrated circuits (ICs) and to adapt the interfaces between existing European IC foundries and newly introduced nano- and micro-technology research activities:
- JRA1 concentrating on Radio-frequency (RF) functionalities;
- JRA2 focusing on sensors added on ICs;
- JRA3 developing new integration blocks of general interest to enable any possible added functionality.
The project management has decided a step-by-step practical approach of collaborative work during the three years of the project:
- The first year was mainly focused on learning to know each other (in terms of facilities, technical teams, specific skills and know-how). Numerous exchanges and group visits were thus performed in advance of the official agenda, in order to launch as soon as possible advanced contacts between the technical teams.
- The second year was dedicated to identifying the complementarities and exploiting them mainly through the definition of specific federative demonstrators, allowing partners to check the merge in real objects of different generic technologies lonely developed.
- The last year of the project has been a very fruitful period of collaboration with the achievement of these common prototypes. The progress on the project was clearly visible both for networking activities and for joint research actions.
Microsystems integration involves the use of typically several different technologies and this is particularly true for RF systems: although there is continuous evolution towards System on chip (SoC) integration, several functionalities require a different technology.
Therefore, the heterogeneous integration of different technologies is required and this integration requires research both on technology development and on design methodologies. The main aim of this work package was to develop the technological capability of integrating wafers and chips from more than one of the partners to working RF microsystems integrated on chips and results in an RF System in a package (SIP).
Five partners (CSEM, IISB-FhG, IMEC, LETI, Tyndall) worked on particular technologies which were built together in a demonstrator module comprising technological blocks from all.
The activities were organised through a two step approach.
During the first 18 months, the focus was put on the development at the different partner laboratories of several technologies and components dedicated to RF applications:
- FhG IISB focused on three-dimenational (3D)-type high density capacitor development and this research work resulted in high density capacitors with a capacitance density increase by a factor of 15 as compared to planar capacitors using the same dielectric thickness. In this work, both technological parameters (dielectric selection, process parameters for deposition and etching etc ) and electrical parameters (capacitance density, resonance frequency) were optimised successfully.
- Tyndall worked on RF MEMS switch technologies and devices.
- Léti worked on a library of components for 'above IC' solutions.
- CSEM worked on Bulk acoustic wave (BAW) resonator devices.
In the second phase (next 18 months), all partners worked together in the design and development of a common RF demonstrator (a 12 GHz radar module) based on merging / integrating technologies and devices from the different partners.
Several RF technologies and components were successfully developed and used to design and realise a 12.8 GHz radar module as a demonstration of the capabilities offered by merging technologies and RF design expertise from CSEM, IISB, IMEC, LETI and Tyndall.
In the area of optical functions, the technologies and contributions from partners were the following:
- Tyndall: SMF fibre compatible silica-on-silicon Photonic lightwave circuit (PLC) design, fabrication and hybrid integration technology.
- CEA-Leti: Sub-micron silicon (a-Si:H) PLCs with light coupling structures and CMOS / Ge-PIN detector technology.
- CSEM: Replicated sol-gel macroscopic mounts (light turning mirrors, fibre holders) design and fabrication technology.
In the area of the development of biochemical sensor on CMOS, the objective was to develop a demonstrator above-IC sensor for biological applications. The partner institutes involved in this work package were CSEM, Tyndall and Léti. For reasons of complementarity and existing technologies in the different institutes, it was decided that the demonstrator should involve avalanche photodiode detection of fluorescence to monitor mammalian cell growth or behaviour, and that the properties of the IC surfaces would be controlled using polypyrrole layers.
MEMS technologies which can be integrated with CMOS have been investigated. A specific demonstrator, namely a resonant accelerometer, is made to check and compare different technologies for integration such as SOI and SiGe technologies. With the SOI technology, MEMS and CMOS can be processed next to each other. Using SiGe at low temperatures (e.g. < or equal to 450 degrees Celsius) on the other hand allows postprocessing MEMS above existing ICs.
The objective of zero level packaging was to offer generic solutions of zero-level packaging including testing methodology. The following was accomplished:
- screening and selection of technologies available amongst the MNT partners. Two different zero-level packaging technologies were identified: thin film encapsulation and hybrid capping.
- identification of key specifications.
- classification of the different technological solutions in tabular format. Additionally, a table with available characterisation techniques was compiled. This included both physical testing (shear strength, hermeticity, outgassing) and electrical testing methods (internal pressure measurement using beam resonators and microbolometers).
- an introductory primer (in PPT) of the technology was compiled focusing on prospective users with a MEMS background but not expertised in the area of zero-level packaging. It describes: general MEMS packaging zero-level requirements, hybrid capping and thin film capping approaches and their comparative (dis)advantages, die-to-wafer and wafer-to-wafer assembly methods and their comparative (dis)advantages, case examples of packaged RF-MEMS devices, hermeticity testing methodogies and their comparative (dis)advantages.
With reference to the growing demand for intelligent integrated power control, especially in mobile systems, integration of power control is a major research topic. But system integration requires advanced power device structures and new manufacturing processes, e.g. for the core components of typical buck / boost DC / DC converters which are power switches and inductors. To show that Tyndall and IISB can provide the technological platform for manufacturing applicable power control systems, the realisation of advanced power switches and an integrable silicon inductor which are hybrid integrated in a demonstrator, was considered. To evaluate the technological basis for power system integration, two types of MOS transistors for different voltage classes were realised: one for low voltage applications (i.e. a voltage of 3.6 V) and the other for medium voltage applications (i.e. a voltage of above 45 V). The second transistor type and the silicon inductor were hybrid integrated in a DC / DC converter system as demonstrator.
To define the device structure and architecture for the 45 V power transistors class, first the device geometry (e.g. depth of wells) was varied and simulated with the focus to optimise the electrical characteristics of the power transistors. Therefore, a triple trench gate structure was used. The simulated improvement in the forward conduction mode using triple gate architecture resulted in a 25 % higher current for identical voltages.
For the proof of concept, single and triple trench gate transistors were manufactured. To compare the single trench gate transistors and the triple trench gate transistors the forward conduction characteristics were measured.
It was shown that it is possible to provide a technological basis for the realisation of power devices for two voltage classes (3.6 V and above 45 V) and passive components for power applications. For the proof of concept, a demonstrator was realised as a system with the devices which are manufactured in research clean rooms at Tyndall Institute (inductor) and FhG-IISB (trench LDMOS). On this technological platform, the devices can be designed and manufactured with advanced system specifications for the use in one application and hopefully in one package as a SIP in the next step. Both transistor types, the trench gate transistor which is manufactured in the clean room of IISB and the 3.6 V transistor which is fabricated in a commercially available technology, can be adapted for this purpose depending on the application.
Organisational and strategic agreements, exchange of people and of knowledge have been undertaken in order to converge towards a definition of common roadmaps. This was the aim of the three networking activities of the project:
1.'Creation of the environment and legal framework to allow the integration of activities' to significantly lower the barriers to collaboration between the participant organisations in particular legal issues and those related to the lack of personal relationships.
2.'Preparing the integration' which focuses on building a common view on the future developments;
3.'Scheduling the exploitation' which organises the operational phase of the alliance: global management, external collaboration, dissemination of the alliance concept.
In parallel, and in order to enhance the alliance platform capabilities and to encourage the interoperability by the creation of a common technology portfolio, three joint research activities have be undertaken, aiming to develop new added functionalities to Integrated circuits (ICs) and to adapt the interfaces between existing European IC foundries and newly introduced nano- and micro-technology research activities:
- JRA1 concentrating on Radio-frequency (RF) functionalities;
- JRA2 focusing on sensors added on ICs;
- JRA3 developing new integration blocks of general interest to enable any possible added functionality.
The project management has decided a step-by-step practical approach of collaborative work during the three years of the project:
- The first year was mainly focused on learning to know each other (in terms of facilities, technical teams, specific skills and know-how). Numerous exchanges and group visits were thus performed in advance of the official agenda, in order to launch as soon as possible advanced contacts between the technical teams.
- The second year was dedicated to identifying the complementarities and exploiting them mainly through the definition of specific federative demonstrators, allowing partners to check the merge in real objects of different generic technologies lonely developed.
- The last year of the project has been a very fruitful period of collaboration with the achievement of these common prototypes. The progress on the project was clearly visible both for networking activities and for joint research actions.
Microsystems integration involves the use of typically several different technologies and this is particularly true for RF systems: although there is continuous evolution towards System on chip (SoC) integration, several functionalities require a different technology.
Therefore, the heterogeneous integration of different technologies is required and this integration requires research both on technology development and on design methodologies. The main aim of this work package was to develop the technological capability of integrating wafers and chips from more than one of the partners to working RF microsystems integrated on chips and results in an RF System in a package (SIP).
Five partners (CSEM, IISB-FhG, IMEC, LETI, Tyndall) worked on particular technologies which were built together in a demonstrator module comprising technological blocks from all.
The activities were organised through a two step approach.
During the first 18 months, the focus was put on the development at the different partner laboratories of several technologies and components dedicated to RF applications:
- FhG IISB focused on three-dimenational (3D)-type high density capacitor development and this research work resulted in high density capacitors with a capacitance density increase by a factor of 15 as compared to planar capacitors using the same dielectric thickness. In this work, both technological parameters (dielectric selection, process parameters for deposition and etching etc ) and electrical parameters (capacitance density, resonance frequency) were optimised successfully.
- Tyndall worked on RF MEMS switch technologies and devices.
- Léti worked on a library of components for 'above IC' solutions.
- CSEM worked on Bulk acoustic wave (BAW) resonator devices.
In the second phase (next 18 months), all partners worked together in the design and development of a common RF demonstrator (a 12 GHz radar module) based on merging / integrating technologies and devices from the different partners.
Several RF technologies and components were successfully developed and used to design and realise a 12.8 GHz radar module as a demonstration of the capabilities offered by merging technologies and RF design expertise from CSEM, IISB, IMEC, LETI and Tyndall.
In the area of optical functions, the technologies and contributions from partners were the following:
- Tyndall: SMF fibre compatible silica-on-silicon Photonic lightwave circuit (PLC) design, fabrication and hybrid integration technology.
- CEA-Leti: Sub-micron silicon (a-Si:H) PLCs with light coupling structures and CMOS / Ge-PIN detector technology.
- CSEM: Replicated sol-gel macroscopic mounts (light turning mirrors, fibre holders) design and fabrication technology.
In the area of the development of biochemical sensor on CMOS, the objective was to develop a demonstrator above-IC sensor for biological applications. The partner institutes involved in this work package were CSEM, Tyndall and Léti. For reasons of complementarity and existing technologies in the different institutes, it was decided that the demonstrator should involve avalanche photodiode detection of fluorescence to monitor mammalian cell growth or behaviour, and that the properties of the IC surfaces would be controlled using polypyrrole layers.
MEMS technologies which can be integrated with CMOS have been investigated. A specific demonstrator, namely a resonant accelerometer, is made to check and compare different technologies for integration such as SOI and SiGe technologies. With the SOI technology, MEMS and CMOS can be processed next to each other. Using SiGe at low temperatures (e.g. < or equal to 450 degrees Celsius) on the other hand allows postprocessing MEMS above existing ICs.
The objective of zero level packaging was to offer generic solutions of zero-level packaging including testing methodology. The following was accomplished:
- screening and selection of technologies available amongst the MNT partners. Two different zero-level packaging technologies were identified: thin film encapsulation and hybrid capping.
- identification of key specifications.
- classification of the different technological solutions in tabular format. Additionally, a table with available characterisation techniques was compiled. This included both physical testing (shear strength, hermeticity, outgassing) and electrical testing methods (internal pressure measurement using beam resonators and microbolometers).
- an introductory primer (in PPT) of the technology was compiled focusing on prospective users with a MEMS background but not expertised in the area of zero-level packaging. It describes: general MEMS packaging zero-level requirements, hybrid capping and thin film capping approaches and their comparative (dis)advantages, die-to-wafer and wafer-to-wafer assembly methods and their comparative (dis)advantages, case examples of packaged RF-MEMS devices, hermeticity testing methodogies and their comparative (dis)advantages.
With reference to the growing demand for intelligent integrated power control, especially in mobile systems, integration of power control is a major research topic. But system integration requires advanced power device structures and new manufacturing processes, e.g. for the core components of typical buck / boost DC / DC converters which are power switches and inductors. To show that Tyndall and IISB can provide the technological platform for manufacturing applicable power control systems, the realisation of advanced power switches and an integrable silicon inductor which are hybrid integrated in a demonstrator, was considered. To evaluate the technological basis for power system integration, two types of MOS transistors for different voltage classes were realised: one for low voltage applications (i.e. a voltage of 3.6 V) and the other for medium voltage applications (i.e. a voltage of above 45 V). The second transistor type and the silicon inductor were hybrid integrated in a DC / DC converter system as demonstrator.
To define the device structure and architecture for the 45 V power transistors class, first the device geometry (e.g. depth of wells) was varied and simulated with the focus to optimise the electrical characteristics of the power transistors. Therefore, a triple trench gate structure was used. The simulated improvement in the forward conduction mode using triple gate architecture resulted in a 25 % higher current for identical voltages.
For the proof of concept, single and triple trench gate transistors were manufactured. To compare the single trench gate transistors and the triple trench gate transistors the forward conduction characteristics were measured.
It was shown that it is possible to provide a technological basis for the realisation of power devices for two voltage classes (3.6 V and above 45 V) and passive components for power applications. For the proof of concept, a demonstrator was realised as a system with the devices which are manufactured in research clean rooms at Tyndall Institute (inductor) and FhG-IISB (trench LDMOS). On this technological platform, the devices can be designed and manufactured with advanced system specifications for the use in one application and hopefully in one package as a SIP in the next step. Both transistor types, the trench gate transistor which is manufactured in the clean room of IISB and the 3.6 V transistor which is fabricated in a commercially available technology, can be adapted for this purpose depending on the application.
