Objective Functional verification is one of the bottlenecks of VLSI-based system design. For economic and industrial reasons, the design of VLSI circuits must be completely validated before manufacturing. Current VLSI validation is still done mainly through the simulation of a limited set of test cases. This does not guarantee correctness. Formal verification methods, on the other hand, are analytic, and avoid the simulation of specific input stimuli. They have the potential to guarantee the correctness of implemented circuits with respect to their specifications for all allowable input stimuli. Fundamental problems still have to be formalised, and efficient domain-specific solutions still need to be found in order to be able to bring formal verification into use for realistically sized applications.The group will address the following topics: efficient basic verification techniques; efficient and automatic verification tools for both synchronous and asynchronous designs; methodologies for designing verifiable circuits; symbolic state-space exploration techniques; verification from lower level (gate and transistor switch) up to higher levels; specification formalisms and provable subsets of HDLs; formal verification from industry-standard VHDL language; integration through a common data model and a common verification methodology; and evaluation of progress in verification technology and methodology through applying both to real chip designs. A multi-disciplinary approach is required. The combination of universities and an electronics research institute gives the appropriate balance between a theoretical approach and one focusing on applied methods. The group will further its objectives through its own internal contact network which will involve meetings of partners active in the above topic areas. The group may organise international workshops in the field of formal hardware design and will participate in workshops involving formal methods and design methodology related topics. POTENTIAL This working group aims to enhance the potential for future technological breakthroughs by identifying novel techniques for the formal verification of the complex VLSI systems that will be required by the European IT industry. The progress of this working group will be regularly presented at international conferences and workshops and in publications. Programme(s) FP3-ESPRIT 3 - Specific research and technological development programme (EEC) in the field of information technologies, 1990-1994 Topic(s) Data not available Call for proposal Data not available Funding Scheme Data not available Coordinator Interuniversitair Mikroelektronica Centrum Address Kapeldreef 75 3030 Heverlee Belgium See on map EU contribution € 0,00 Participants (5) Sort alphabetically Sort by EU Contribution Expand all Collapse all JOHANN WOLFGANG GOETHE UNIVERSITAET FRANKFURT Germany EU contribution € 0,00 Address Robert-mayer strasse 8-10 60325 Frankfurt-am-main See on map POLITECNICO DI TORINO Italy EU contribution € 0,00 Address Corso duca degli abruzzi 24 10129 Torino See on map UNIVERSITY OF STRATHCLYDE United Kingdom EU contribution € 0,00 Address 16 richmond street G1 IXQ Glasgow See on map Université d'Aix-Marseille I (Université de Provence) France EU contribution € 0,00 Address 3 place victor hugo 13331 Marseille See on map Université de Grenoble I (Université Joseph Fourier) France EU contribution € 0,00 Address 385 avenue de la bibliothèque 38041 Grenoble See on map
