Objetivo Functional verification is one of the bottlenecks of VLSI-based system design. For economic and industrial reasons, the design of VLSI circuits must be completely validated before manufacturing. Current VLSI validation is still done mainly through the simulation of a limited set of test cases. This does not guarantee correctness. Formal verification methods, on the other hand, are analytic, and avoid the simulation of specific input stimuli. They have the potential to guarantee the correctness of implemented circuits with respect to their specifications for all allowable input stimuli. Fundamental problems still have to be formalised, and efficient domain-specific solutions still need to be found in order to be able to bring formal verification into use for realistically sized applications.The group will address the following topics: efficient basic verification techniques; efficient and automatic verification tools for both synchronous and asynchronous designs; methodologies for designing verifiable circuits; symbolic state-space exploration techniques; verification from lower level (gate and transistor switch) up to higher levels; specification formalisms and provable subsets of HDLs; formal verification from industry-standard VHDL language; integration through a common data model and a common verification methodology; and evaluation of progress in verification technology and methodology through applying both to real chip designs. A multi-disciplinary approach is required. The combination of universities and an electronics research institute gives the appropriate balance between a theoretical approach and one focusing on applied methods. The group will further its objectives through its own internal contact network which will involve meetings of partners active in the above topic areas. The group may organise international workshops in the field of formal hardware design and will participate in workshops involving formal methods and design methodology related topics. POTENTIAL This working group aims to enhance the potential for future technological breakthroughs by identifying novel techniques for the formal verification of the complex VLSI systems that will be required by the European IT industry. The progress of this working group will be regularly presented at international conferences and workshops and in publications. Programa(s) FP3-ESPRIT 3 - Specific research and technological development programme (EEC) in the field of information technologies, 1990-1994 Tema(s) Data not available Convocatoria de propuestas Data not available Régimen de financiación Data not available Coordinador Interuniversitair Mikroelektronica Centrum Aportación de la UE Sin datos Dirección Kapeldreef 75 3030 Heverlee Bélgica Ver en el mapa Coste total Sin datos Participantes (5) Ordenar alfabéticamente Ordenar por aportación de la UE Ampliar todo Contraer todo JOHANN WOLFGANG GOETHE UNIVERSITAET FRANKFURT Alemania Aportación de la UE Sin datos Dirección Robert-Mayer strasse 8-10 60325 Frankfurt-am-Main Ver en el mapa Coste total Sin datos POLITECNICO DI TORINO Italia Aportación de la UE Sin datos Dirección CORSO DUCA DEGLI ABRUZZI 24 10129 TORINO Ver en el mapa Coste total Sin datos UNIVERSITY OF STRATHCLYDE Reino Unido Aportación de la UE Sin datos Dirección 16 RICHMOND STREET G1 IXQ GLASGOW Ver en el mapa Coste total Sin datos Université d'Aix-Marseille I (Université de Provence) Francia Aportación de la UE Sin datos Dirección 3 place Victor Hugo 13331 Marseille Ver en el mapa Coste total Sin datos Université de Grenoble I (Université Joseph Fourier) Francia Aportación de la UE Sin datos Dirección 385 avenue de la Bibliothèque 38041 Grenoble Ver en el mapa Coste total Sin datos
