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Content archived on 2024-04-19

Multilayer Integrated Devices in Advanced Silicon


The goal of MIDAS is to strengthen the European knowledge base in the area of high-performance silicon microelectronics. The technical objective is to demonstrate the performance enhancement in bipolar transistors by using new materials such as silicon-germanium, new processing techniques such as low-temperature epitaxy, and selected deposition and new device concepts such as heterojunction bipolar transistors. The demonstration of the potential will be done by a combination of performance prediction based on device simulations using data derived from test structures, and the fabrication of bipolar transistors.
A range of different technologies, such as molecular beam epitaxy (MBE), ultrahigh vacuum chemical vapour deposition (UHV-CVD) and plasma assisted chemical vapour deposition (CVD) are being used and compared in terms of material quality, growth sequence and time. Aspects of integration of epitaxial growth of silicon (Si) and silicon germanide (SiGe) by the different techniques, using selective and nonselective growth, are being investigated.

The first operating transistors have been made. These are meant either to optimize the dopant and/or germanium profiles, or to optimize the device structure to obtain low parasitics. Excellent results in terms of high frequency performance have been obtained for deposited base transistors. In the modelling area, the missing material parameters, in particular for SiGe, have been identified, and the influence on calculated performance has been evaluated.
Silicon multilayer technology will improve performance characteristics of bipolar devices in terms of speed, noise, linearity and power consumption. It will also create silicon heterojunction devices with additional degrees of freedom with respect to device design and optimisation as compared with homojunction devices. This additional degree of freedom can be used to improve the speed with transit frequencies up to the 100 GHz range, or to improve the analogue features at "moderate" transit frequencies of 20 to 50 GHz.

The technical targets of the project are:

simulated optimised devices
Silicon bipolar homo-devices

Propagation delay minimum <20 ps
Minimum power delay product <10 fJ
Effective emitter width <0.5 micron
Transit frequency 25-60 GHz

Silicon bipolar hetero-devices

Propagation delay minimum <15 ps
Minimum power delay product <20 fJ
Noise figure at 2 GHz <1.5 dB
(using standard transistor)
Effective emitter width <0.5 micron
Transit frequency 50-100 GHz
Maximum oscillation frequency 50-100 GHz
Linearity: early voltage >20 V

fabricated non-optimised devices

Silicon bipolar homo-devices

Transit frequency > 25 GHz
Base pinch resistance <25 kW
Noise figure at 2 GHz <2 dB

Silicon bipolar hetero-devices

Transit frequency 25-50 GHz
Base pinch resistance 10 kW
Noise figure at 2 GHz <1.5 dB
Early voltage >20 V


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Participants (8)