Hierarchical Optical Interconnects for Computer Systems

Informazioni relative al progetto

HOLICS

ID dell’accordo di sovvenzione: 6276

Progetto chiuso

Data di avvio 1 Aprile 1992

Data di completamento 31 Marzo 1995

Finanziato da

• Specific research and technological development programme (EEC) in the field of information technologies, 1990-1994

Costo totale

Nessun dato

Contributo UE

Nessun dato

Coordinato da

GEC Marconi Materials Technology Ltd
United Kingdom

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Risultati sfruttabili

Optical interconnects for hierarchical computer systems

In hierarchical computer systems, conventionally the interconnection is handled via parallel electrical busses. Although the latest high performance structures such as the JIAWG parallel interface bus (PI-bus) can operate over 58 electrical bus lines and handle total data and control rates in excess of 500 Mbits/s (when implemented at full specification), they are physically dense structures which are intrinsically unreliable. The aim of the HOLICS project is to develop optoelectronic technology to alleviate these problems, with a new approach based on board mounted optoelectronic drivers communicating directly over polymer waveguide backplanes. The main focus was to design and assemble a fully functional, high speed, EMC (electromagnetic compatability) tolerant, optically interconnected processor cluster consisting of a set of high speed processors and associated circuitry, interconnected via an optical backplane. Once validated, this cluster system was used in a complete hierarchical computer demonstrator within HOLICS. Technically, the key development was the design and realization of optoelectronic transceivers, implemented as a multichip module assembly. They are constructed using a silicon substrate housed in an all silicon hermetic package and incorporate a number of novel features, which results in a compact low profile surface mount package. A robust, custom single chip ECL receiver was also specifically designed by ETH Zurich, providing high gain and a wide dynamic range, and capable of operating over a wide range of supply voltages and environmental conditions. These transceiver modules have exceptionally high sensitivity (-29 dBm at 500 Mbits/s for 10E9 bit error rate), low power consumption (700 mW for full transceiver mode) and very low crosstalk (equivalent to -50 dB of internal attenuation) and can replace existing electronic interconnect systems in backplane links, local board to board links and global links.