First year period summary
During this period, the basis of the project were set up with the description of the requirements and architecture of the future PHY. The design of the first test chip was developed. The goal of this phase was to prototype the most critical blocks of the Ethernet Transceiver, especially for 10BASET, which was achieved. However, the available Multi Project Wafer fabrication windows had a slight modification w.r.t the ones originally conceived in the proposal and so the phase 1 tape-out suffered a slight delay which implied that the overall project planning suffered a small deviation.
Second year period summary
The main goals in the second year were, on one hand to manufacture and test the test chip 1 (also known as TC1) and, on the other hand to reach a high level of maturity on the final device so that the target manufacturing goal of SEPHY could be achieved.
With respect to the first goal, the TC1 was successfully manufactured, assembled and preliminary tested for continuity and consumption with results in line with the expectations. In addition to that, a versatile and complex test setup was developed to allow testing the TC1 in standalone mode (to validate the TC1 blocks) and also in system mode in combination with an external FPGA where the digital code that will be included on SEPHY final chip could be preliminary validated.
Regarding the second goal, a huge effort were put in the design and simulation tasks in order to get a mature chip.
Final period summary
In the frame of the project an engineering module of an Ethernet 10/100 PHY transceiver was developed. It has been proved to be fully functional up to 20m in both 10BASET and 100BASE-TX modes with a very good radiation performance. The radiation testing of chip also showed very good performance. In terms of TID, the validation proved that the functionality of the parts is not affected at all up to the maximum dose tested (111 krad). With respect to the SEE radiation tests performed, the parts showed to be insensitive to latch-up up to the maximum energy used (62 MeVcm2/mg). In addition to that, the parts were sensitive to SEU/SET but with a very competitive BER and with a predicted SEU rate (GEO) considered to be low for standard GEO space programs. The network level tests were also satisfactory. The final SEPHY device was placed on a dedicated TTEthernet Equipment were a detailed suite of test cases, including Rate Constrained, Regular and Time Triggered Ethernet traffic, was successfully passed.
The EM developed will require minor upgrades before qualification basically to update configuration registers and ease the startup procedure, but in any case, they can be tested by interested parties upon request.
In term of the exploitation and commercialization, considering the SEPHY condition of radiation-hardened device, the proposed PHY transceiver mainly targets applications in the space sector. Nevertheless, the deterministic Ethernet protocol is quickly expanding to critical applications in other sectors, such as aviation, railway or nuclear.
The main results of the device are:
- Integrated high performance 100 Mb/s clock recovery circuitry requiring no external filters up to 20m.
- Full Duplex support for 10 and 100 Mb/s.
- Programmable loopback modes for easy system diagnostics.
- 3.3V/1.8V power supply.
- Extended temperature range from -55°C to 125°C.
- MII/RMII MAC communication interface.
- MI interface for MAC management and diagnostics.
- 15 years lifetime at maximum operating conditions.
- TID hardness greater than 100krad.
- SEU threshold LET>30MeV· cm²/mg.
- SEU Error Rate lower than 10e-10 errors/bit-day (@ <62 MeV· cm²/mg).
- SEL Threshold LET greater than 62 MeV· cm²/mg.
