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NEUral computing aRchitectures in Advanced Monolithic 3D-VLSI nano-technologies

Deliverables

Physical Level and Computational Level benchmarking.

Physical Level and Computational Level benchmarking.

Electrical characterization of 1T-1R RRAM cell as input for compact modeling for WP 2

Electrical characterization of 1T-1R RRAM cell as input for compact modeling for WP2

Joint publication on hardware compatible recurrent neural network architecture.

Joint publication on hardware compatible recurrent neural network architecture.

Report on the characteristics of TFT’s as interconnects for a Global Synapse Chips

Report on the characteristics of TFT’s as interconnects for a Global Synapse Chips

Report on spike-based learning circuits suitable for RRAM technologies.

Report on spike-based learning circuits suitable for RRAM technologies.

Process description for the integration of RRAM technology in 28nm FDSOI BEOL, as input for WP 3

Process description for the integration of RRAM technology in 28nm FDSOI BEOL, as input for WP 3

Report on digital spike-based computing circuits suitable for RRAM technologies

Report on digital spike-based computing circuits suitable for RRAM technologies

Project web-site on line with public and restricted areas

Project web-site on line with public and restricted areas

Design ready for tape-out of the FDSOI 28nm multi-core spiking neural network chip.

Design ready for tape-out of the FDSOI 28nm multi-core spiking neural network chip.

Toolbox of algorithms and computational architecture building blocks.

Toolbox of algorithms and computational architecture building blocks.

Searching for OpenAIRE data...

Publications

Spike-driven threshold-based learning with memristive synapses and neuromorphic silicon neurons

Author(s): E Covi, R George, J Frascaroli, S Brivio, C Mayr, H Mostafa, G Indiveri, S Spiga
Published in: Journal of Physics D: Applied Physics, Issue 51/34, 2018, Page(s) 344003, ISSN 0022-3727
DOI: 10.1088/1361-6463/aad361

Evidence of soft bound behaviour in analogue memristive devices for neuromorphic computing

Author(s): Jacopo Frascaroli, Stefano Brivio, Erika Covi, Sabina Spiga
Published in: Scientific Reports, Issue 8/1, 2018, ISSN 2045-2322
DOI: 10.1038/s41598-018-25376-x

Extended memory lifetime in spiking neural networks employing memristive synapses with nonlinear conductance dynamics

Author(s): S Brivio, D Conti, M V Nair, J Frascaroli, E Covi, C Ricciardi, G Indiveri, S Spiga
Published in: Nanotechnology, Issue 30/1, 2019, Page(s) 015102, ISSN 0957-4484
DOI: 10.1088/1361-6528/aae81c

Stimulated Ionic Telegraph Noise in Filamentary Memristive Devices

Author(s): Stefano Brivio, Jacopo Frascaroli, Erika Covi, Sabina Spiga
Published in: Scientific Reports, Issue 9/1, 2019, Page(s) 6310, ISSN 2045-2322
DOI: 10.1038/s41598-019-41497-3

Computing optimal discrete readout weights in reservoir computing is NP-hard

Author(s): Fatemeh Hadaeghi, Herbert Jaeger
Published in: Neurocomputing, Issue 338, 2019, Page(s) 233-236, ISSN 0925-2312
DOI: 10.1016/j.neucom.2019.02.009

Organizing Sequential Memory in a Neuromorphic Device Using Dynamic Neural Fields

Author(s): Raphaela Kreiser, Dora Aathmani, Ning Qiao, Giacomo Indiveri, Yulia Sandamirskaya
Published in: Frontiers in Neuroscience, Issue 12, 2018, ISSN 1662-453X
DOI: 10.3389/fnins.2018.00717

An Ultralow Leakage Synaptic Scaling Homeostatic Plasticity Circuit With Configurable Time Scales up to 100 ks

Author(s): Ning Qiao, Chiara Bartolozzi, Giacomo Indiveri
Published in: IEEE Transactions on Biomedical Circuits and Systems, Issue 11/6, 2017, Page(s) 1271-1277, ISSN 1932-4545
DOI: 10.1109/tbcas.2017.2754383

A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Author(s): Saber Moradi, Ning Qiao, Fabio Stefanini, Giacomo Indiveri
Published in: IEEE Transactions on Biomedical Circuits and Systems, Issue 12/1, 2018, Page(s) 106-122, ISSN 1932-4545
DOI: 10.1109/TBCAS.2017.2759700

A differential memristive synapse circuit for on-line learning in neuromorphic computing systems

Author(s): Manu V Nair, Lorenz K Muller, Giacomo Indiveri
Published in: Nano Futures, Issue 1/3, 2017, Page(s) 035003, ISSN 2399-1984
DOI: 10.1088/2399-1984/aa954a

Calibration of offset via bulk for low-power HfO2 based 1T1R memristive crossbar read-out system

Author(s): C. Mohan, L.A. Camuñas-Mesa, E. Vianello, L. Periniolla, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona, B. Linares-Barranco
Published in: Microelectronic Engineering, Issue 198, 2018, Page(s) 35-47, ISSN 0167-9317
DOI: 10.1016/j.mee.2018.06.011

Active Perception With Dynamic Vision Sensors. Minimum Saccades With Optimum Recognition

Author(s): Amirreza Yousefzadeh, Garrick Orchard, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
Published in: IEEE Transactions on Biomedical Circuits and Systems, Issue 12/4, 2018, Page(s) 927-939, ISSN 1932-4545
DOI: 10.1109/tbcas.2018.2834428

Memristors fire away

Author(s): Bernabe Linares-Barranco
Published in: Nature Electronics, Issue 1/2, 2018, Page(s) 100-101, ISSN 2520-1131
DOI: 10.1038/s41928-018-0028-x

On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

Author(s): Amirreza Yousefzadeh, Evangelos Stromatias, Miguel Soto, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
Published in: Frontiers in Neuroscience, Issue 12, 2018, ISSN 1662-453X
DOI: 10.3389/fnins.2018.00665

Event-Driven Stereo Visual Tracking Algorithm to Solve Object Occlusion

Author(s): Luis A. Camunas-Mesa, Teresa Serrano-Gotarredona, Sio-Hoi Ieng, Ryad Benosman, Bernabe Linares-Barranco
Published in: IEEE Transactions on Neural Networks and Learning Systems, Issue 29/9, 2018, Page(s) 4223-4237, ISSN 2162-237X
DOI: 10.1109/tnnls.2017.2759326

On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems

Author(s): Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabe Linares-Barranco
Published in: IEEE Transactions on Biomedical Circuits and Systems, Issue 11/5, 2017, Page(s) 1133-1147, ISSN 1932-4545
DOI: 10.1109/tbcas.2017.2717341

Power-Accuracy Trade-Offs for Heartbeat Classification on Neural Networks Hardware

Author(s): Adarsha Balaji, Federico Corradi, Anup Das, Sandeep Pande, Siebren Schaafsma, Francky Catthoor
Published in: Journal of Low Power Electronics, Issue 14/4, 2018, Page(s) 508-519, ISSN 1546-1998
DOI: 10.1166/jolpe.2018.1582

Unsupervised heart-rate estimation in wearables with Liquid states and a probabilistic readout

Author(s): Anup Das, Paruthi Pradhapan, Willemijn Groenendaal, Prathyusha Adiraju, Raj Thilak Rajan, Francky Catthoor, Siebren Schaafsma, Jeffrey L. Krichmar, Nikil Dutt, Chris Van Hoof
Published in: Neural Networks, Issue 99, 2018, Page(s) 134-147, ISSN 0893-6080
DOI: 10.1016/j.neunet.2017.12.015

Energy-Efficient Mapping of LTE-A PHY Signal Processing Tasks on Microservers

Author(s): Anup Das, Francky Catthoor, Andre Bourdoux, Bert Gyselinckx
Published in: IEEE Transactions on Green Communications and Networking, Issue 2/2, 2018, Page(s) 397-407, ISSN 2473-2400
DOI: 10.1109/tgcn.2018.2794477

An Event-Driven Classifier for Spiking Neural Networks Fed with Synthetic or Dynamic Vision Sensor Data

Author(s): Evangelos Stromatias, Miguel Soto, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
Published in: Frontiers in Neuroscience, Issue 11, 2017, ISSN 1662-453X
DOI: 10.3389/fnins.2017.00350

Stochastic circuit breaker network model for bipolar resistance switching memories

Author(s): S. Brivio, S. Spiga
Published in: Journal of Computational Electronics, 2017, Page(s) 1-13, ISSN 1569-8025
DOI: 10.1007/s10825-017-1055-y

Role of Al doping in the filament disruption in HfO<sub>2</sub> resistance switches

Author(s): Stefano Brivio, Jacopo Frascaroli, Sabina Spiga
Published in: Nanotechnology, 2017, ISSN 0957-4484
DOI: 10.1088/1361-6528/aa8013

Overcoming Catastrophic Interference using Conceptor-Aided Backpropagation

Author(s): X. He, H. Jaeger
Published in: Proc. International Conference on Learning Representations 2018 (ICLR 2018), 2018

Reservoir Transfer on Analog Neuromorphic Hardware

Author(s): Xu He, Tianlin Liu, Fatemeh Hadaeghi, Herbert Jaeger
Published in: 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 2019, Page(s) 1234-1238
DOI: 10.1109/ner.2019.8716891

A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems

Author(s): Ning Qiao, Giacomo Indiveri
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5
DOI: 10.1109/iscas.2018.8351623

A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems

Author(s): Ning Qiao, Giacomo Indiveri
Published in: 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2018, Page(s) 93-101
DOI: 10.1109/async.2018.00028

Analog circuits for mixed-signal neuromorphic computing architectures in 28 nm FD-SOI technology

Author(s): Ning Qiao, Giacomo Indiveri
Published in: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017, Page(s) 1-4
DOI: 10.1109/s3s.2017.8309203

Self-Testing Analog Spiking Neuron Circuit

Author(s): Sarah A. El-Sayed, Luis A. Camunas-Mesa, Bernabe Linares-Barranco, Haralampos-G. Stratigopoulos
Published in: 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2019, Page(s) 81-84
DOI: 10.1109/smacd.2019.8795234

A Current Attenuator for Efficient Memristive Crossbars Read-Out

Author(s): Charanraj Mohan, Jose M. de la Rosa, Elisa Vianello, Luca Perniola, Carlo Reita, Bernabe Linares-Barranco, Teresa Serrano-Gotarredona
Published in: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, Page(s) 1-5
DOI: 10.1109/iscas.2019.8702604

Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma-delta quantization

Author(s): Amirreza Yousefzadeh, Sahar Hosseini, Priscila Holanda, Sam Leroux, Thilo Werner, Teresa Serrano-Gotarredona, Bernabe Linares Barranco, Bart Dhoedt, Pieter Simoens
Published in: 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2019, Page(s) 81-85
DOI: 10.1109/aicas.2019.8771624

An Intrinsic Method for Fast Parameter Update on the SpiNNaker Platform

Author(s): M. Soto, T. Serrano-Gotarredona, B. Linares-Barranco
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5
DOI: 10.1109/iscas.2018.8351476

Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA

Author(s): L. A. Camunas-Mesa, Y. Dominguez-Cordero, T. Serrano-Gotarredona, B. Linares-Barranco
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5
DOI: 10.1109/iscas.2018.8351570

Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker

Author(s): Amirreza Yousefzadeh, Mikel Soto, Teresa Serrano-Gotarredona, Francesco Galluppi, Luis Plana, Steve Furber, Bernabe Linares-Barranco
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-4
DOI: 10.1109/iscas.2018.8350990

Hybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network

Author(s): Amirreza Yousefzadeh, Garrick Orchard, Evangelos Stromatias, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5
DOI: 10.1109/iscas.2018.8351562

Bulk-based DC offset calibration for low-power memristor array read-out system

Author(s): Charanraj Mohan, Luis A. Camunas-Mesa, Elisa Vianello, Luca Perniola, Carlo Reita, Jose M. de la Rosa, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
Published in: 2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS), 2017, Page(s) 1-5
DOI: 10.1109/dcis.2017.8311626

Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems

Author(s): A. Yousefzadeh, M. Jablonski, T. Iakymchuk, A. Linares-Barranco, A. Rosado, L. A. Plana, T. Serrano-Gotarredona, S. Furber, B. Linares-Barranco
Published in: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Page(s) 1-4
DOI: 10.1109/iscas.2017.8050802

Hardware implementation of convolutional STDP for on-line visual feature learning

Author(s): A. Yousefzadeh, T. Masquelier, T. Serrano-Gotarredona, B. Linares-Barranco
Published in: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Page(s) 1-4
DOI: 10.1109/iscas.2017.8050870

Heartbeat Classification in Wearables Using Multi-layer Perceptron and Time-Frequency Joint Distribution of ECG

Author(s): Anup Kumar Das ; Francky Catthoor ; Siebren Schaafsma
Published in: IEEE/ACM International Conference on Connected Health: Applications, Systems and Engineering Technologies (CHASE), 2018

Design-technology co-optimization for OxRRAM-based synaptic processing unit

Author(s): A. Mallik, D. Garbin, A. Fantini, D. Rodopoulos, R. Degraeve, J. Stuijt, A. K. Das, S. Schaafsma, P. Debacker, G. Donadio, H. Hody, L. Goux, G. S. Kar, A. Furnemont, A. Mocuta, P. Raghavan
Published in: 2017 Symposium on VLSI Technology, 2017, Page(s) T178-T179
DOI: 10.23919/vlsit.2017.7998166

On the Use of Offset Calibration Techniques for Low-Power Memristor Arrays Read-Out




Automatic gain control of ultra-low leakage synaptic scaling homeostatic plasticity circuits

Author(s): Ning Qiao, Giacomo Indiveri, Chiara Bartolozzi
Published in: 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2016, Page(s) 156-159
DOI: 10.1109/BioCAS.2016.7833755

Scaling mixed-signal neuromorphic processors to 28 nm FD-SOI technologies

Author(s): Ning Qiao, Giacomo Indiveri
Published in: 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2016, Page(s) 552-555
DOI: 10.1109/BioCAS.2016.7833854

An auto-scaling wide dynamic range current to frequency converter for real-time monitoring of signals in neuromorphic systems

Author(s): Ning Qiao, Giacomo Indiveri
Published in: 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2016, Page(s) 160-163
DOI: 10.1109/BioCAS.2016.7833756

Neuromorphic Electronic Systems for Reservoir Computing

Author(s): F. Hadaeghi
Published in: Reservoir Computing: Theory, Physical Implementations and Applications, 2019

Very Large Scale Neuromorphic Systems For Biological Signal Processing

Author(s): Francky Catthoor, Srinjoy Mitra, Anup Das and Siebren Schaafsma
Published in: CMOS Circuits for Biological Sensing and Processing Systems, 2017

Unconventional Information Processing Systems, Novel Hardware: A Tour d’Horizon

Author(s): Hadaeghi, F. and He, X. and Jaeger, H.
Published in: 2017

Overcoming Catastrophic Interference by Conceptors

Author(s): He, Xu and Jaeger, Herbert
Published in: 2017

Exploration of segmented bus architecture for neuromorphic computing

Author(s): Yuefeng Wu
Published in: 2017

Exploration of general purpose interface for spiking-based application simulator

Author(s): Prathyusha Adiraju
Published in: 2017