NEUral computing aRchitectures in Advanced Monolithic 3D-VLSI nano-technologies

Informations projet

NeuRAM3

N° de convention de subvention: 687299

DOI

10.3030/687299

Projet clôturé

Date de signature de la CE 26 Octobre 2015

Date de début 1 Janvier 2016

Date de fin 30 Juin 2019

Financé au titre de

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Coût total

€ 4 181 015,00

Contribution de l’UE

€ 3 216 150,00

Coordonné par

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
France

CORDIS fournit des liens vers les livrables publics et les publications des projets HORIZON.

Les liens vers les livrables et les publications des projets du 7e PC, ainsi que les liens vers certains types de résultats spécifiques tels que les jeux de données et les logiciels, sont récupérés dynamiquement sur OpenAIRE .

Livrables

Documents, reports (7)

Physical Level and Computational Level benchmarking.
Electrical characterization of 1T-1R RRAM cell as input for compact modeling for WP 2

Electrical characterization of 1T-1R RRAM cell as input for compact modeling for WP2

Joint publication on hardware compatible recurrent neural network architecture.
Report on the characteristics of TFT’s as interconnects for a Global Synapse Chips
Report on spike-based learning circuits suitable for RRAM technologies.
Process description for the integration of RRAM technology in 28nm FDSOI BEOL, as input for WP 3
Report on digital spike-based computing circuits suitable for RRAM technologies

Other (3)

Project web-site on line with public and restricted areas

Project website on line with public and restricted areas

Design ready for tape-out of the FDSOI 28nm multi-core spiking neural network chip.
Toolbox of algorithms and computational architecture building blocks.

Publications

Peer reviewed articles (21)

Spike-driven threshold-based learning with memristive synapses and neuromorphic silicon neurons

Auteurs: E Covi, R George, J Frascaroli, S Brivio, C Mayr, H Mostafa, G Indiveri, S Spiga
Publié dans: Journal of Physics D: Applied Physics, Numéro 51/34, 2018, Page(s) 344003, ISSN 0022-3727
Éditeur: Institute of Physics Publishing
DOI: 10.1088/1361-6463/aad361

Evidence of soft bound behaviour in analogue memristive devices for neuromorphic computing

Auteurs: Jacopo Frascaroli, Stefano Brivio, Erika Covi, Sabina Spiga
Publié dans: Scientific Reports, Numéro 8/1, 2018, ISSN 2045-2322
Éditeur: Nature Publishing Group
DOI: 10.1038/s41598-018-25376-x

Extended memory lifetime in spiking neural networks employing memristive synapses with nonlinear conductance dynamics

Auteurs: S Brivio, D Conti, M V Nair, J Frascaroli, E Covi, C Ricciardi, G Indiveri, S Spiga
Publié dans: Nanotechnology, Numéro 30/1, 2019, Page(s) 015102, ISSN 0957-4484
Éditeur: Institute of Physics Publishing
DOI: 10.1088/1361-6528/aae81c

Stimulated Ionic Telegraph Noise in Filamentary Memristive Devices

Auteurs: Stefano Brivio, Jacopo Frascaroli, Erika Covi, Sabina Spiga
Publié dans: Scientific Reports, Numéro 9/1, 2019, Page(s) 6310, ISSN 2045-2322
Éditeur: Nature Publishing Group
DOI: 10.1038/s41598-019-41497-3

Computing optimal discrete readout weights in reservoir computing is NP-hard

Auteurs: Fatemeh Hadaeghi, Herbert Jaeger
Publié dans: Neurocomputing, Numéro 338, 2019, Page(s) 233-236, ISSN 0925-2312
Éditeur: Elsevier BV
DOI: 10.1016/j.neucom.2019.02.009

Organizing Sequential Memory in a Neuromorphic Device Using Dynamic Neural Fields

Auteurs: Raphaela Kreiser, Dora Aathmani, Ning Qiao, Giacomo Indiveri, Yulia Sandamirskaya
Publié dans: Frontiers in Neuroscience, Numéro 12, 2018, ISSN 1662-453X
Éditeur: Frontiers in
DOI: 10.3389/fnins.2018.00717

An Ultralow Leakage Synaptic Scaling Homeostatic Plasticity Circuit With Configurable Time Scales up to 100 ks

Auteurs: Ning Qiao, Chiara Bartolozzi, Giacomo Indiveri
Publié dans: IEEE Transactions on Biomedical Circuits and Systems, Numéro 11/6, 2017, Page(s) 1271-1277, ISSN 1932-4545
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tbcas.2017.2754383

A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Auteurs: Saber Moradi, Ning Qiao, Fabio Stefanini, Giacomo Indiveri
Publié dans: IEEE Transactions on Biomedical Circuits and Systems, Numéro 12/1, 2018, Page(s) 106-122, ISSN 1932-4545
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TBCAS.2017.2759700

A differential memristive synapse circuit for on-line learning in neuromorphic computing systems

Auteurs: Manu V Nair, Lorenz K Muller, Giacomo Indiveri
Publié dans: Nano Futures, Numéro 1/3, 2017, Page(s) 035003, ISSN 2399-1984
Éditeur: IOP Publishing Ltd
DOI: 10.1088/2399-1984/aa954a

Calibration of offset via bulk for low-power HfO2 based 1T1R memristive crossbar read-out system

Auteurs: C. Mohan, L.A. Camuñas-Mesa, E. Vianello, L. Periniolla, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona, B. Linares-Barranco
Publié dans: Microelectronic Engineering, Numéro 198, 2018, Page(s) 35-47, ISSN 0167-9317
Éditeur: Elsevier BV
DOI: 10.1016/j.mee.2018.06.011

Active Perception With Dynamic Vision Sensors. Minimum Saccades With Optimum Recognition

Auteurs: Amirreza Yousefzadeh, Garrick Orchard, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
Publié dans: IEEE Transactions on Biomedical Circuits and Systems, Numéro 12/4, 2018, Page(s) 927-939, ISSN 1932-4545
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tbcas.2018.2834428

Memristors fire away

Auteurs: Bernabe Linares-Barranco
Publié dans: Nature Electronics, Numéro 1/2, 2018, Page(s) 100-101, ISSN 2520-1131
Éditeur: Nature
DOI: 10.1038/s41928-018-0028-x

On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

Auteurs: Amirreza Yousefzadeh, Evangelos Stromatias, Miguel Soto, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
Publié dans: Frontiers in Neuroscience, Numéro 12, 2018, ISSN 1662-453X
Éditeur: Frontiers
DOI: 10.3389/fnins.2018.00665

Event-Driven Stereo Visual Tracking Algorithm to Solve Object Occlusion

Auteurs: Luis A. Camunas-Mesa, Teresa Serrano-Gotarredona, Sio-Hoi Ieng, Ryad Benosman, Bernabe Linares-Barranco
Publié dans: IEEE Transactions on Neural Networks and Learning Systems, Numéro 29/9, 2018, Page(s) 4223-4237, ISSN 2162-237X
Éditeur: IEEE Computational Intelligence Society
DOI: 10.1109/tnnls.2017.2759326

On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems

Auteurs: Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabe Linares-Barranco
Publié dans: IEEE Transactions on Biomedical Circuits and Systems, Numéro 11/5, 2017, Page(s) 1133-1147, ISSN 1932-4545
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tbcas.2017.2717341

Power-Accuracy Trade-Offs for Heartbeat Classification on Neural Networks Hardware

Auteurs: Adarsha Balaji, Federico Corradi, Anup Das, Sandeep Pande, Siebren Schaafsma, Francky Catthoor
Publié dans: Journal of Low Power Electronics, Numéro 14/4, 2018, Page(s) 508-519, ISSN 1546-1998
Éditeur: American Scientific Publishers
DOI: 10.1166/jolpe.2018.1582

Unsupervised heart-rate estimation in wearables with Liquid states and a probabilistic readout

Auteurs: Anup Das, Paruthi Pradhapan, Willemijn Groenendaal, Prathyusha Adiraju, Raj Thilak Rajan, Francky Catthoor, Siebren Schaafsma, Jeffrey L. Krichmar, Nikil Dutt, Chris Van Hoof
Publié dans: Neural Networks, Numéro 99, 2018, Page(s) 134-147, ISSN 0893-6080
Éditeur: Pergamon Press Ltd.
DOI: 10.1016/j.neunet.2017.12.015

Energy-Efficient Mapping of LTE-A PHY Signal Processing Tasks on Microservers

Auteurs: Anup Das, Francky Catthoor, Andre Bourdoux, Bert Gyselinckx
Publié dans: IEEE Transactions on Green Communications and Networking, Numéro 2/2, 2018, Page(s) 397-407, ISSN 2473-2400
Éditeur: IEEE
DOI: 10.1109/tgcn.2018.2794477

An Event-Driven Classifier for Spiking Neural Networks Fed with Synthetic or Dynamic Vision Sensor Data

Auteurs: Evangelos Stromatias, Miguel Soto, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
Publié dans: Frontiers in Neuroscience, Numéro 11, 2017, ISSN 1662-453X
Éditeur: Frontiers Media S.A.
DOI: 10.3389/fnins.2017.00350

Stochastic circuit breaker network model for bipolar resistance switching memories

Auteurs: S. Brivio, S. Spiga
Publié dans: Journal of Computational Electronics, 2017, Page(s) 1-13, ISSN 1569-8025
Éditeur: Kluwer Academic Publishers
DOI: 10.1007/s10825-017-1055-y

Role of Al doping in the filament disruption in HfO₂ resistance switches

Auteurs: Stefano Brivio, Jacopo Frascaroli, Sabina Spiga
Publié dans: Nanotechnology, 2017, ISSN 0957-4484
Éditeur: Institute of Physics Publishing
DOI: 10.1088/1361-6528/aa8013

Conference proceedings (23)

Overcoming Catastrophic Interference using Conceptor-Aided Backpropagation

Auteurs: X. He, H. Jaeger
Publié dans: Proc. International Conference on Learning Representations 2018 (ICLR 2018), 2018
Éditeur: ICLR

Reservoir Transfer on Analog Neuromorphic Hardware

Auteurs: Xu He, Tianlin Liu, Fatemeh Hadaeghi, Herbert Jaeger
Publié dans: 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 2019, Page(s) 1234-1238, ISBN 978-1-5386-7921-0
Éditeur: IEEE
DOI: 10.1109/ner.2019.8716891

A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems

Auteurs: Ning Qiao, Giacomo Indiveri
Publié dans: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5, ISBN 978-1-5386-4881-0
Éditeur: IEEE
DOI: 10.1109/iscas.2018.8351623

A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems

Auteurs: Ning Qiao, Giacomo Indiveri
Publié dans: 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2018, Page(s) 93-101, ISBN 978-1-5386-5883-3
Éditeur: IEEE
DOI: 10.1109/async.2018.00028

Analog circuits for mixed-signal neuromorphic computing architectures in 28 nm FD-SOI technology

Auteurs: Ning Qiao, Giacomo Indiveri
Publié dans: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017, Page(s) 1-4, ISBN 978-1-5386-3766-1
Éditeur: IEEE
DOI: 10.1109/s3s.2017.8309203

Self-Testing Analog Spiking Neuron Circuit

Auteurs: Sarah A. El-Sayed, Luis A. Camunas-Mesa, Bernabe Linares-Barranco, Haralampos-G. Stratigopoulos
Publié dans: 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2019, Page(s) 81-84, ISBN 978-1-7281-1201-5
Éditeur: IEEE
DOI: 10.1109/smacd.2019.8795234

Learning weights with STDP to build prototype images for classification

Auteurs: Ajay Vasudevan, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
Publié dans: 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2019, Page(s) 1-5, ISBN 978-1-7281-3424-6
Éditeur: IEEE
DOI: 10.1109/dtis.2019.8734907

A Current Attenuator for Efficient Memristive Crossbars Read-Out

Auteurs: Charanraj Mohan, Jose M. de la Rosa, Elisa Vianello, Luca Perniola, Carlo Reita, Bernabe Linares-Barranco, Teresa Serrano-Gotarredona
Publié dans: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, Page(s) 1-5, ISBN 978-1-7281-0397-6
Éditeur: IEEE
DOI: 10.1109/iscas.2019.8702604

Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma-delta quantization

Auteurs: Amirreza Yousefzadeh, Sahar Hosseini, Priscila Holanda, Sam Leroux, Thilo Werner, Teresa Serrano-Gotarredona, Bernabe Linares Barranco, Bart Dhoedt, Pieter Simoens
Publié dans: 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2019, Page(s) 81-85, ISBN 978-1-5386-7884-8
Éditeur: IEEE
DOI: 10.1109/aicas.2019.8771624

An Intrinsic Method for Fast Parameter Update on the SpiNNaker Platform

Auteurs: M. Soto, T. Serrano-Gotarredona, B. Linares-Barranco
Publié dans: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5, ISBN 978-1-5386-4881-0
Éditeur: IEEE
DOI: 10.1109/iscas.2018.8351476

Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA

Auteurs: L. A. Camunas-Mesa, Y. Dominguez-Cordero, T. Serrano-Gotarredona, B. Linares-Barranco
Publié dans: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5, ISBN 978-1-5386-4881-0
Éditeur: IEEE
DOI: 10.1109/iscas.2018.8351570

Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker

Auteurs: Amirreza Yousefzadeh, Mikel Soto, Teresa Serrano-Gotarredona, Francesco Galluppi, Luis Plana, Steve Furber, Bernabe Linares-Barranco
Publié dans: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-4, ISBN 978-1-5386-4881-0
Éditeur: IEEE
DOI: 10.1109/iscas.2018.8350990

Hybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network

Auteurs: Amirreza Yousefzadeh, Garrick Orchard, Evangelos Stromatias, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
Publié dans: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5, ISBN 978-1-5386-4881-0
Éditeur: IEEE
DOI: 10.1109/iscas.2018.8351562

Bulk-based DC offset calibration for low-power memristor array read-out system

Auteurs: Charanraj Mohan, Luis A. Camunas-Mesa, Elisa Vianello, Luca Perniola, Carlo Reita, Jose M. de la Rosa, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
Publié dans: 2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS), 2017, Page(s) 1-5, ISBN 978-1-5386-5108-7
Éditeur: IEEE
DOI: 10.1109/dcis.2017.8311626

Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems

Auteurs: A. Yousefzadeh, M. Jablonski, T. Iakymchuk, A. Linares-Barranco, A. Rosado, L. A. Plana, T. Serrano-Gotarredona, S. Furber, B. Linares-Barranco
Publié dans: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Page(s) 1-4, ISBN 978-1-4673-6853-7
Éditeur: IEEE
DOI: 10.1109/iscas.2017.8050802

Hardware implementation of convolutional STDP for on-line visual feature learning

Auteurs: A. Yousefzadeh, T. Masquelier, T. Serrano-Gotarredona, B. Linares-Barranco
Publié dans: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Page(s) 1-4, ISBN 978-1-4673-6853-7
Éditeur: IEEE
DOI: 10.1109/iscas.2017.8050870

Mapping of local and global synapses on spiking neuromorphic hardware

Auteurs: Anup Das, Yuefeng Wu, Khanh Huynh, Francesco Dell'Anna, Francky Catthoor, Siebren Schaafsma
Publié dans: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Page(s) 1217-1222, ISBN 978-3-9819263-0-9
Éditeur: IEEE
DOI: 10.23919/date.2018.8342201

Heartbeat Classification in Wearables Using Multi-layer Perceptron and Time-Frequency Joint Distribution of ECG

Auteurs: Anup Kumar Das ; Francky Catthoor ; Siebren Schaafsma
Publié dans: IEEE/ACM International Conference on Connected Health: Applications, Systems and Engineering Technologies (CHASE), 2018, ISBN 978-1-5386-7206-8
Éditeur: IEEE

Design-technology co-optimization for OxRRAM-based synaptic processing unit

Auteurs: A. Mallik, D. Garbin, A. Fantini, D. Rodopoulos, R. Degraeve, J. Stuijt, A. K. Das, S. Schaafsma, P. Debacker, G. Donadio, H. Hody, L. Goux, G. S. Kar, A. Furnemont, A. Mocuta, P. Raghavan
Publié dans: 2017 Symposium on VLSI Technology, 2017, Page(s) T178-T179, ISBN 978-4-86348-605-8
Éditeur: IEEE
DOI: 10.23919/vlsit.2017.7998166

On the Use of Offset Calibration Techniques for Low-Power Memristor Arrays Read-Out

Auteurs: C. Mohan, T. Serrano-Gotarredona, E. Vianello, L. Perniolla, C. Reita, J.M. de la Rosa, B. Linares-Barranco
Publié dans: International Conference on Memristive Materials, Devices & Systems (MEMRISYS 2017), Numéro biannual, 2017
Éditeur: IEEE

Automatic gain control of ultra-low leakage synaptic scaling homeostatic plasticity circuits

Auteurs: Ning Qiao, Giacomo Indiveri, Chiara Bartolozzi
Publié dans: 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2016, Page(s) 156-159, ISBN 978-1-5090-2959-4
Éditeur: IEEE
DOI: 10.1109/BioCAS.2016.7833755

Scaling mixed-signal neuromorphic processors to 28 nm FD-SOI technologies

Auteurs: Ning Qiao, Giacomo Indiveri
Publié dans: 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2016, Page(s) 552-555, ISBN 978-1-5090-2959-4
Éditeur: IEEE
DOI: 10.1109/BioCAS.2016.7833854

An auto-scaling wide dynamic range current to frequency converter for real-time monitoring of signals in neuromorphic systems

Auteurs: Ning Qiao, Giacomo Indiveri
Publié dans: 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2016, Page(s) 160-163, ISBN 978-1-5090-2959-4
Éditeur: IEEE
DOI: 10.1109/BioCAS.2016.7833756

Book chapters (2)

Neuromorphic Electronic Systems for Reservoir Computing

Auteurs: F. Hadaeghi
Publié dans: Reservoir Computing: Theory, Physical Implementations and Applications, 2019
Éditeur: Springer Verlag

Very Large Scale Neuromorphic Systems For Biological Signal Processing

Auteurs: Francky Catthoor, Srinjoy Mitra, Anup Das and Siebren Schaafsma
Publié dans: CMOS Circuits for Biological Sensing and Processing Systems, 2017
Éditeur: Springer

Other (2)

Unconventional Information Processing Systems, Novel Hardware: A Tour d’Horizon

Auteurs: Hadaeghi, F. and He, X. and Jaeger, H.
Publié dans: 2017
Éditeur: Jacobs University Bremen

Overcoming Catastrophic Interference by Conceptors

Auteurs: He, Xu and Jaeger, Herbert
Publié dans: 2017
Éditeur: Jacobs University Bremen

Thesis and dissertations (2)

Exploration of segmented bus architecture for neuromorphic computing

Auteurs: Yuefeng Wu
Publié dans: 2017
Éditeur: Techn.Univ.Eindhoven

Exploration of general purpose interface for spiking-based application simulator

Auteurs: Prathyusha Adiraju
Publié dans: 2017
Éditeur: Techn.Univ.Eindhoven