Periodic Reporting for period 2 - GREAT (heteroGeneous integRated magnetic tEchnology using multifunctional standardized sTack (MSS))
Reporting period: 2017-07-01 to 2019-06-30
The interest for developing smart systems based on interconnected objects is growing fast. It is assumed that 50 billion objects will be connected in 2020. The main components of “Internet of Things” (IoT) devices are autonomous battery-operated smart embedded systems comprising RF circuits for communications, digital circuits for data processing, memory for data storage and analog circuits such as sensors, filters, converters, cameras, GPS systems... Consequently, the key requirements for IoT devices are ultra-low power, high processing capabilities, wireless communication and autonomy. In battery-operated Machine to Machine (M2M) and Machine to Human (M2H) operations, the processing cycle includes sleep, wake-up, sense, store, process and send actions. With smart connected objects or mobile devices used as terminals, the need to store and access an increasing amount of data requires energy-efficient embedded architectures. However, the continuously decreasing size of devices and increasing operation frequency lead to critical power consumption and heating issues.
As pointed out by the ITRS, one of the best solutions to stop this trend is the modification of the memory hierarchy by the integration of non-volatile memories like Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), which would immediately minimize static power and pave the way towards normally-off/instant-on computing. Moreover, the Magnetic Tunnel Junctions (MTJs), basic elements of MRAMs, can also be used as RF emitter/receiver and magnetic field sensor. However, so far, MTJs are optimized to perform each function independently. Using the same device for all the functions would allow integrating them in the same chip. To tackle the key issues of monolithic heterogeneous integration, the goal of the GREAT project is to co-integrate multiple functions like sensors, RF receivers and logic/memory together within CMOS by adapting the STT-MTJs to a single baseline technology enabling logic, memory, and analog functions in the same System-on-Chip (SoC), as the enabling technology platform for M2M and M2H IoT. This will lead to a unique cell technology called Multifunctional Standardized Stack (MSS). Thus, GREAT will achieve the same goal as heterogeneous integration but in a much simpler way since the it will enable different functions using the same technology.
As pointed out by the ITRS, one of the best solutions to stop this trend is the modification of the memory hierarchy by the integration of non-volatile memories like Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), which would immediately minimize static power and pave the way towards normally-off/instant-on computing. Moreover, the Magnetic Tunnel Junctions (MTJs), basic elements of MRAMs, can also be used as RF emitter/receiver and magnetic field sensor. However, so far, MTJs are optimized to perform each function independently. Using the same device for all the functions would allow integrating them in the same chip. To tackle the key issues of monolithic heterogeneous integration, the goal of the GREAT project is to co-integrate multiple functions like sensors, RF receivers and logic/memory together within CMOS by adapting the STT-MTJs to a single baseline technology enabling logic, memory, and analog functions in the same System-on-Chip (SoC), as the enabling technology platform for M2M and M2H IoT. This will lead to a unique cell technology called Multifunctional Standardized Stack (MSS). Thus, GREAT will achieve the same goal as heterogeneous integration but in a much simpler way since the it will enable different functions using the same technology.
During the first period, the MSS stack has been successfully defined. The memory functionality has been validated with an offset issue in the hysteresis cycle still to be solved. Two sensor concepts have been proposed, which have been validated using the same stack, proving the co-integrability of the two functions. Concerning the RF function, very good results were obtained, but with a stack slightly different. This is very encouraging, but we still have to confirm its co-integrability. The post-process of the magnetic back-end above CMOS wafers was a little bit delayed due to technology issues, which are now fixed. Micromagnetic simulations have been carried-out, with a focus on the RF functionality. These simulations confirm predict oscillations with conditions very similar to the ones of experiments. All the design tools have been provided, based on the technology information. IPs blocks have been designed and integrated in the digital design flow. Analog functions based on MSS have been studied and designed. A full flow for evaluating hybrid systems was developed. It covers all the levels of design, from circuit to system. An open-source tool called MAGPIE was made available to the scientific community, and a variability-aware memory estimation and design tool was also proposed.
During the second period, the technology was transfered to TowerJazz. The second demonstrator was designed and sent to fabrication. From the first charcterization results, the process was optimized, in particular to solve the offset in the hysteresis cycle. At this stage, an implementation error was detected, making the fdemonstrator non-functional. The choice has been made to use a backup lot from Tower to fabricate a second version of the second demonstrator, with the improved technology and implementation issue fixed.
Then, an intensive test of this last run was carried out, giving very promising results:
- The three functionalities have been demonstrated using the same MSS stack.
- Several circuits were partially functional: half of the MSS MRAM was fully functional. For RF and analog functions, we could make CMOS or magnetic parts operate individually. Preliminary results for the System on Chip show that it is possible to load a program in the SoC and make it run, with reapeatble reading/writing between the processor and the MSS-MRAM. These results prove that the process is operating correctly, with a good yield and possible co-integration with CMOS.
During the extension of the project, it was decided to focus on the collaboration with the Advisory Board, in particular with Electronics Marin and Agriscope. A specific memory was designed, according to the specifications of EM, and a model was generated and integrated in the design flow to evaluate the advantages of the full MRAM solutions compared to standard approaches using Flash and/or SRAM. Very encouraging results were obtained, which raised the interest of EM who provided a letter of interest for the project. The same flow was used to evaluate the MRAM use for use-cases provided by Agriscope and showing also very encouraging results.
During the second period, the technology was transfered to TowerJazz. The second demonstrator was designed and sent to fabrication. From the first charcterization results, the process was optimized, in particular to solve the offset in the hysteresis cycle. At this stage, an implementation error was detected, making the fdemonstrator non-functional. The choice has been made to use a backup lot from Tower to fabricate a second version of the second demonstrator, with the improved technology and implementation issue fixed.
Then, an intensive test of this last run was carried out, giving very promising results:
- The three functionalities have been demonstrated using the same MSS stack.
- Several circuits were partially functional: half of the MSS MRAM was fully functional. For RF and analog functions, we could make CMOS or magnetic parts operate individually. Preliminary results for the System on Chip show that it is possible to load a program in the SoC and make it run, with reapeatble reading/writing between the processor and the MSS-MRAM. These results prove that the process is operating correctly, with a good yield and possible co-integration with CMOS.
During the extension of the project, it was decided to focus on the collaboration with the Advisory Board, in particular with Electronics Marin and Agriscope. A specific memory was designed, according to the specifications of EM, and a model was generated and integrated in the design flow to evaluate the advantages of the full MRAM solutions compared to standard approaches using Flash and/or SRAM. Very encouraging results were obtained, which raised the interest of EM who provided a letter of interest for the project. The same flow was used to evaluate the MRAM use for use-cases provided by Agriscope and showing also very encouraging results.
"A lot of investigations about the advantages of spintronics have been carried-out, mainly on the digital side, but also for sensor and RF applications. To our knowledge, it is the first project in Europe with a global vision at the system level, and including digital, analog and sensing MRAM technologies to empower high-end wireless IoT. This 2.5D integration approach will solve many issues of the standard 3D integration scheme:
• Since all functions are embedded in a single silicon chip, heat dissipation is overly simplified, performance improved and power consumption reduced;
• With only 4 or 5 additional masks, the additional cost of our technology is around 15%, much lower than with 3D.
This will contribute to strongly improve the performances of smart devices. Our challenge is clearly to reach aggressive objectives especially in terms of:
• Manufacturing costs (mask number divided by 3),
• Density (by a factor up to 6),
• Ultra-low power consumption (global reduction by a factor of x3 to x5 and ""0"" power in idle mode),
• Reliability.
This progress beyond the State of the Art, in a market as wide as IoT, will help improving the competitiveness of Europe against USA, Japan and Korea where massive public investment has been made in order to safeguard their positions, given the strategic importance of the microelectronics industry for their economies.
From the societal point of view, it will improve the employment by offering a unique production capability in Europe, with related equipment, processes and design know-how. It will also enlarge semiconductor and magnetic research facilities and skills, and will train engineers and technicians on these fields. The huge power consumption savings allowed by the technology will contribute to preserve the environment and the future generation of security and health devices and applications (such as biosensors, environment screening, etc.) will contribute to improve the quality of life.
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• Since all functions are embedded in a single silicon chip, heat dissipation is overly simplified, performance improved and power consumption reduced;
• With only 4 or 5 additional masks, the additional cost of our technology is around 15%, much lower than with 3D.
This will contribute to strongly improve the performances of smart devices. Our challenge is clearly to reach aggressive objectives especially in terms of:
• Manufacturing costs (mask number divided by 3),
• Density (by a factor up to 6),
• Ultra-low power consumption (global reduction by a factor of x3 to x5 and ""0"" power in idle mode),
• Reliability.
This progress beyond the State of the Art, in a market as wide as IoT, will help improving the competitiveness of Europe against USA, Japan and Korea where massive public investment has been made in order to safeguard their positions, given the strategic importance of the microelectronics industry for their economies.
From the societal point of view, it will improve the employment by offering a unique production capability in Europe, with related equipment, processes and design know-how. It will also enlarge semiconductor and magnetic research facilities and skills, and will train engineers and technicians on these fields. The huge power consumption savings allowed by the technology will contribute to preserve the environment and the future generation of security and health devices and applications (such as biosensors, environment screening, etc.) will contribute to improve the quality of life.
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