"The overall work is sub-divided into the following three project stages:
1. Self-assembly of single Si NDs in SiO2 films based on ion beam mixing at interfaces
It was experimentally confirmed, that – as predicted so far only by simulations – self-assembly of single Si nanodots is possible by phase separation of SiOx if the mixed volume is < 500 nm³. At first, this approach has been experimentally validated by local irradiation of a Si/SiO2/Si layer stack using FIB equipment. In connection with Si/SiO2/Si nanopillars, broad beam Si implantation and subsequent rapid thermal annealing have been applied. The experimental optimization of parameters like oxide thickness, nanodot size, mixing conditions or thermal budget has been guided by extensive computer simulations of ion beam mixing, phase separation and ND formation. Suitable parameters have been found to enable the reliable formation of Si quantum dots < 3nm in a thin SiO2 disc with tunneling distances < 1 nm between the Si ND and the drain and source regions.
2. Process development for sub-30 nm NPs from stacked Si/SiO2/Si
Two approaches were investigated: (i) Electron Beam Lithography (EBL) and Reactive Ion Etching (RIE) and, (ii) Directed Self-Assembly Technology (DSA). Finally, the EBL/RIE approach was used to fabricate almost cylindrical Si/SiO2/Si nanopillars with a diameter close to 20 nm. Further shrinking to a targeted size of 10 - 12 nm is possible by sacrificial oxidation using the low-temperature plasma oxidation technique. Stand-alone Si/SiO2/Si pillars of 10 nm diameter and 70 nm height with Si NDs in the oxide have been successfully prepared on 200 mm wafer level ready to be integrated in the SET process flow.
3. Technology development for a gate-all-around SET and a hybrid SET/FET device
Processes and methods for the CMOS compatible integration of SET devices based on of nanodots/nanopillars that can later be transferred to an industrial foundry were elaborated. A suitable CMOS compatible process flow to fabricate stand-alone SETs and an integrated SET/FET circuit have been defined. For SET fabrication in gate-all-around configuration, the use of hydrogen-silsesquioxane (HSQ) for the intermediate insulating layers and titanium nitride (TiN) as gate electrode are key technological steps. It has been shown that SET and FET can be integrated on SOI substrates and that existing nanopillars/noanodots survive the FET.
4. Management, dissemination and exploitation activities
The project is characterized by a close interaction of predictive simulation work, process development, preparation of test and device components and frontier metrology. To evaluate and support the project progress, an industry endorsement board with renowned partners from Globalfoundries, XFAB, Infineon Technologies, and ARKEMA have been installed. Project results are mainly disseminated by peer-reviewed publications (26), contributions at international conferences and workshops (95), other public presentations (36), public communications and newsletters (12) as well as two international workshops (2017: “Formation of 3D nanostructures by ions beams”; 2018: ""Directed-self assembly using block copolymer technology""). Exploitation of project results include the development of new simulation, new polymer materials for directed self-assembly or CMOS compatible solutions for nanopillar, nanodot and SET fabrication, which are partly ready for technology transfer with TRL > 4."
