Periodic Reporting for period 3 - IONS4SET (Ion-irradiation-induced Si Nanodot Self-Assembly for Hybrid SET-CMOS Technology)
Período documentado: 2019-02-01 hasta 2020-07-31
Billions of tiny computers (www.gartner.com) that can sense and communicate from anywhere are coming online, creating the “Internet of Things” (IoT). Despite their continuously extended functionalities, low-power consumption of these mobile devices is required to enable sufficiently long operation time. The development of energy saving devices and technical equipment is a key task to enable future economic growth while avoiding detrimental effects on nature and climate.
Electronic microprocessors mainly consist of electric switches called field-effect transistors (FET). Future transistor generations will be made by nanowires or, if looking to real 3D microcircuit architectures, by vertical nanopillars. Within IONS4SET, for the first time a Single Electron Transistor (SET) – characterized by extremely low energy dissipation – will be realized on the basis of a very tiny silicon (Si) nanodot embedded in the oxide of a stacked Si/SiO2/Si nanopillar. The IONS4SET project aims to demonstrate that such SETs work at room-temperature and can be mass-produced with current semiconductor (CMOS) technology which is far beyond the state of the art. The project approach combines bottom-up (Si nanodot self-assembly) and top-down (electron-beam lithography and reactive ion etching) technologies which fully fits the requirements of future 3D device architectures. Besides technology development, the project advances the scientific understanding the electrical characteristics of SETs, as well as understanding fundamental effects in nanofabrication occurring at extremely small device dimensions. For this purpose, advanced metrology and characterization as well as scientific modelling and computer simulations are applied to predict process parameters and to explain electrical behavior.
IONS4SET demonstrates that its innovation has a realistic chance to pave the way for an industrial large-scale fabrication of SETs, as integration is fully CMOS-compatible and key components were successfully realized. However, cutting-edge equipment and well-developed process technologies have to be used to fulfil the extreme requirements of device integration.
Electronic microprocessors mainly consist of electric switches called field-effect transistors (FET). Future transistor generations will be made by nanowires or, if looking to real 3D microcircuit architectures, by vertical nanopillars. Within IONS4SET, for the first time a Single Electron Transistor (SET) – characterized by extremely low energy dissipation – will be realized on the basis of a very tiny silicon (Si) nanodot embedded in the oxide of a stacked Si/SiO2/Si nanopillar. The IONS4SET project aims to demonstrate that such SETs work at room-temperature and can be mass-produced with current semiconductor (CMOS) technology which is far beyond the state of the art. The project approach combines bottom-up (Si nanodot self-assembly) and top-down (electron-beam lithography and reactive ion etching) technologies which fully fits the requirements of future 3D device architectures. Besides technology development, the project advances the scientific understanding the electrical characteristics of SETs, as well as understanding fundamental effects in nanofabrication occurring at extremely small device dimensions. For this purpose, advanced metrology and characterization as well as scientific modelling and computer simulations are applied to predict process parameters and to explain electrical behavior.
IONS4SET demonstrates that its innovation has a realistic chance to pave the way for an industrial large-scale fabrication of SETs, as integration is fully CMOS-compatible and key components were successfully realized. However, cutting-edge equipment and well-developed process technologies have to be used to fulfil the extreme requirements of device integration.
"The overall work is sub-divided into the following three project stages:
1. Self-assembly of single Si NDs in SiO2 films based on ion beam mixing at interfaces
It was experimentally confirmed, that – as predicted so far only by simulations – self-assembly of single Si nanodots is possible by phase separation of SiOx if the mixed volume is < 500 nm³. At first, this approach has been experimentally validated by local irradiation of a Si/SiO2/Si layer stack using FIB equipment. In connection with Si/SiO2/Si nanopillars, broad beam Si implantation and subsequent rapid thermal annealing have been applied. The experimental optimization of parameters like oxide thickness, nanodot size, mixing conditions or thermal budget has been guided by extensive computer simulations of ion beam mixing, phase separation and ND formation. Suitable parameters have been found to enable the reliable formation of Si quantum dots < 3nm in a thin SiO2 disc with tunneling distances < 1 nm between the Si ND and the drain and source regions.
2. Process development for sub-30 nm NPs from stacked Si/SiO2/Si
Two approaches were investigated: (i) Electron Beam Lithography (EBL) and Reactive Ion Etching (RIE) and, (ii) Directed Self-Assembly Technology (DSA). Finally, the EBL/RIE approach was used to fabricate almost cylindrical Si/SiO2/Si nanopillars with a diameter close to 20 nm. Further shrinking to a targeted size of 10 - 12 nm is possible by sacrificial oxidation using the low-temperature plasma oxidation technique. Stand-alone Si/SiO2/Si pillars of 10 nm diameter and 70 nm height with Si NDs in the oxide have been successfully prepared on 200 mm wafer level ready to be integrated in the SET process flow.
3. Technology development for a gate-all-around SET and a hybrid SET/FET device
Processes and methods for the CMOS compatible integration of SET devices based on of nanodots/nanopillars that can later be transferred to an industrial foundry were elaborated. A suitable CMOS compatible process flow to fabricate stand-alone SETs and an integrated SET/FET circuit have been defined. For SET fabrication in gate-all-around configuration, the use of hydrogen-silsesquioxane (HSQ) for the intermediate insulating layers and titanium nitride (TiN) as gate electrode are key technological steps. It has been shown that SET and FET can be integrated on SOI substrates and that existing nanopillars/noanodots survive the FET.
4. Management, dissemination and exploitation activities
The project is characterized by a close interaction of predictive simulation work, process development, preparation of test and device components and frontier metrology. To evaluate and support the project progress, an industry endorsement board with renowned partners from Globalfoundries, XFAB, Infineon Technologies, and ARKEMA have been installed. Project results are mainly disseminated by peer-reviewed publications (26), contributions at international conferences and workshops (95), other public presentations (36), public communications and newsletters (12) as well as two international workshops (2017: “Formation of 3D nanostructures by ions beams”; 2018: ""Directed-self assembly using block copolymer technology""). Exploitation of project results include the development of new simulation, new polymer materials for directed self-assembly or CMOS compatible solutions for nanopillar, nanodot and SET fabrication, which are partly ready for technology transfer with TRL > 4."
1. Self-assembly of single Si NDs in SiO2 films based on ion beam mixing at interfaces
It was experimentally confirmed, that – as predicted so far only by simulations – self-assembly of single Si nanodots is possible by phase separation of SiOx if the mixed volume is < 500 nm³. At first, this approach has been experimentally validated by local irradiation of a Si/SiO2/Si layer stack using FIB equipment. In connection with Si/SiO2/Si nanopillars, broad beam Si implantation and subsequent rapid thermal annealing have been applied. The experimental optimization of parameters like oxide thickness, nanodot size, mixing conditions or thermal budget has been guided by extensive computer simulations of ion beam mixing, phase separation and ND formation. Suitable parameters have been found to enable the reliable formation of Si quantum dots < 3nm in a thin SiO2 disc with tunneling distances < 1 nm between the Si ND and the drain and source regions.
2. Process development for sub-30 nm NPs from stacked Si/SiO2/Si
Two approaches were investigated: (i) Electron Beam Lithography (EBL) and Reactive Ion Etching (RIE) and, (ii) Directed Self-Assembly Technology (DSA). Finally, the EBL/RIE approach was used to fabricate almost cylindrical Si/SiO2/Si nanopillars with a diameter close to 20 nm. Further shrinking to a targeted size of 10 - 12 nm is possible by sacrificial oxidation using the low-temperature plasma oxidation technique. Stand-alone Si/SiO2/Si pillars of 10 nm diameter and 70 nm height with Si NDs in the oxide have been successfully prepared on 200 mm wafer level ready to be integrated in the SET process flow.
3. Technology development for a gate-all-around SET and a hybrid SET/FET device
Processes and methods for the CMOS compatible integration of SET devices based on of nanodots/nanopillars that can later be transferred to an industrial foundry were elaborated. A suitable CMOS compatible process flow to fabricate stand-alone SETs and an integrated SET/FET circuit have been defined. For SET fabrication in gate-all-around configuration, the use of hydrogen-silsesquioxane (HSQ) for the intermediate insulating layers and titanium nitride (TiN) as gate electrode are key technological steps. It has been shown that SET and FET can be integrated on SOI substrates and that existing nanopillars/noanodots survive the FET.
4. Management, dissemination and exploitation activities
The project is characterized by a close interaction of predictive simulation work, process development, preparation of test and device components and frontier metrology. To evaluate and support the project progress, an industry endorsement board with renowned partners from Globalfoundries, XFAB, Infineon Technologies, and ARKEMA have been installed. Project results are mainly disseminated by peer-reviewed publications (26), contributions at international conferences and workshops (95), other public presentations (36), public communications and newsletters (12) as well as two international workshops (2017: “Formation of 3D nanostructures by ions beams”; 2018: ""Directed-self assembly using block copolymer technology""). Exploitation of project results include the development of new simulation, new polymer materials for directed self-assembly or CMOS compatible solutions for nanopillar, nanodot and SET fabrication, which are partly ready for technology transfer with TRL > 4."
The progress of IONS4SET beyond the state of the art is demonstarted by the following results:
1. Stacked Si/SiO2/Si nanopillars down to 10 nm diameter and > 50 nm height were fabricated using standard CMOS microelectronic technologies.
2. Theoretically predicted single Si nanodot formation in the oxide of a stacked Si/SiO2/Si nanopillar has been validated fo the first time.
3. Stacked nanopillars with embedded Si nanodots as key functional SET components are compatible with the thermal, chemical and mechanical stress involved in the complex process flow of SET and FET fabrication.
4. A complete CMOS-compatible process flow for SET fabrication based on vertically stacked Si/SiO2/Si nanopillar transistors has been elaborated. Fully contacted SETs have been fabricated and tested.
5. Fabrication of a hybrid SET/FET device has been performed and confirm the possibility combine SET fabrication with other device technologies which may include FETs, ASICs or mixed-modules.
The project IONS4SET covers advanced research on TRLs 2 to 4. IONS4SET provides main solutions for SETs based on vertically stacked nanopillars, even in cases where a potential foundry in detail prefers other solutions for lithography, intermetal dielectrics or metal contact formation.
Socio-economic impact will arise if low-power products based on results developed in IONS4SET will be on the market.
1. Stacked Si/SiO2/Si nanopillars down to 10 nm diameter and > 50 nm height were fabricated using standard CMOS microelectronic technologies.
2. Theoretically predicted single Si nanodot formation in the oxide of a stacked Si/SiO2/Si nanopillar has been validated fo the first time.
3. Stacked nanopillars with embedded Si nanodots as key functional SET components are compatible with the thermal, chemical and mechanical stress involved in the complex process flow of SET and FET fabrication.
4. A complete CMOS-compatible process flow for SET fabrication based on vertically stacked Si/SiO2/Si nanopillar transistors has been elaborated. Fully contacted SETs have been fabricated and tested.
5. Fabrication of a hybrid SET/FET device has been performed and confirm the possibility combine SET fabrication with other device technologies which may include FETs, ASICs or mixed-modules.
The project IONS4SET covers advanced research on TRLs 2 to 4. IONS4SET provides main solutions for SETs based on vertically stacked nanopillars, even in cases where a potential foundry in detail prefers other solutions for lithography, intermetal dielectrics or metal contact formation.
Socio-economic impact will arise if low-power products based on results developed in IONS4SET will be on the market.