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Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node

Periodic Reporting for period 1 - SUPERAID7 (Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node)

Reporting period: 2016-01-01 to 2017-06-30

Among the physical limitations which challenge progress in nanoelectronics for aggressively scaled More Moore, process variability is getting ever more critical. Effects from various sources of process variations, both systematic and stochastic, influence each other and lead to variations of the electrical, thermal and mechanical behavior of devices, interconnects and circuits. Correlations are of key importance because they drastically affect the percentage of products which meet the specifications. Whereas the comprehensive experimental investigation of these effects is largely impossible, modelling and simulation (TCAD) offers the unique possibility to predefine process variations and trace their effects on subsequent process steps and on devices and circuits fabricated, just by changing the corresponding input data. This important requirement for and capability of simulation is among others highlighted in the International Technology Roadmap for Semiconductors ITRS.
SUPERAID7 builds upon the successful FP7 project SUPERTHEME which focused on advanced More-than-Moore devices, and establishes a software system for the simulation of the impact of systematic and statistical process variations on advanced More Moore devices and circuits down to the 7 nm node and below, including especially interconnects. This needs improved physical models and extended compact models. Device architectures addressed in the benchmarks include especially TriGate/ΩGate FETs and stacked nanowires, including alternative channel materials. The software developed will be benchmarked utilizing background and sideground experiments of the partner CEA. Main channels for exploitation will be software commercialization via the partner GSS and support of device architecture activities at CEA. Furthermore, an Industrial Advisory Board will contribute to the specifications and will get early access to the project results.
WP1 “Project Management” standard management actions were carried out.
WP2 “Specifications and Benchmarks” is dedicated to the key features of the simulation system from the point of view of exploitation beyond the project. Specifications were defined for 7nm Trigate (FinFET) and 5nm Stacked-Nanowires MOSFET technology to be simulated. Morphological data and associated measured electrical characteristics for these devices have been described in order to perform process and device simulation in WP3/WP4. Comparison between experimental data and simulation are made.
The work of WP3 “Variation-Aware Equipment and Process Simulation” was focused on the integration of the topography modules from Fraunhofer IISB and TU Wien (lithography, etching, deposition) and on the development of physical models for topography steps. The latter is based on an analysis of the current capabilities of the modules and the resulting requirements for adaptations with respect to the SUPERAID7 benchmarks but also with respect to needs from the simulation end-user community as a whole.
In WP4 “Variation-Aware Device and Interconnect Simulation” a set of confined scattering models and a ballistic version of a Non-Equilibrium Green's Function Simulator have been developed. Ab-initio quantum simulations of surface roughness with realistic More-Moore device parameters obtained from CEA-LETI has been successfully completed. A fast field solver has been developed that can be used to extract resistances and capacitances for advanced interconnect structures. This includes the capability to model global and statistical local variability due to line edge roughness and metal granularity.
In WP5 “Software Integration and Variation-Aware Compact Models” the integration of the GSS interconnect simulator with output from the lithography/topography simulation tools from Fraunhofer and TU Wien has been achieved and a predictive and physical compact model (LETI-NSP) for Gate-All-Around (GAA) stacked NanoWire/NanoSheet (NW/NS) MOSFET has been developed by the CEA-LETI. GSS enabled the use of custom apps in Sentaurus Workbench and improvements to GSS Enigma to greatly improve the integration and usability of the GSS Design Technology Co-Optimization (DTCO) flow. The Leti-NSP compact model is now integrated in the GSS compact model extractor, Mystic.
Within WP6 “Dissemination” the SUPERAID7 WWW page has been set up. Besides this several papers on results from SUPERAID7 were already published, and several presentations made at conferences and workshops.
First results from SUPERAID7 could already be commercialized. This includes especially the GSS integrated DTCO flow already made commercially available from Synopsys. Furthermore, the LETI-NSP compact model is being proposed for international standardization via the compact model coalition (CMC) to allow for the inclusion of LETI-NSP in all major ECAD tools.
In the following the progress and expected results are outlined for the four technical work packages WP2 to WP5.

The results obtained in WP2 summarize, for the first time, a very detailed database on morphological/electrical results of Trigate nanowiredevices. The electron and hole transport is described for both unstrained and (tensile/compressive) strain Si and SiGe channels. For the first time, the Precession Electron Diffraction (PED) technique, with a nm-scale precision, has been used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process.
The current set of SUPERAID7 topography modules developed and improved in WP3 allows the simulation of integrated topography process sequences using various levels of physical modeling for all steps involved, that is, lithography, etching, and deposition. The possibility to run them in an integrated environment and to provide the structures to device and interconnect simulation is – to our knowledge – beyond state-of-the-art.
Within WP4 an advanced stochastic multi-subband device simulator based on a set of quantum confinement aware scattering models has been developed. A quantum simulator accounting for source-to-drain tunneling which includes parameters obtained from first-principle (DFT) approaches and computes current and charge in mode space has been successfully validated. The reliability of novel interconnect geometries is analyzed using state-of-the-art models for the process-induced and electromigration-induced stresses.
Within WP5 a fully integrated tool flow has been developed by GSS. The integration of the tool flow with Synopsys Sentaurus Workbench (SWB) will be improved and used to generate a full design-technology co-optimisation (DTCO) flow with devices based on the design of CEA-Leti in WP2. Full global and local statistical variability in devices and interconnects will be included through to circuit simulation. CEA-LETI developed the “LETI-NSP model” which is the first compact model for GAA stacked-Nanowire/Nanosheet MOSFET able to consider a wide range of cross section shapes (circular, square, rectangular, …) with a correct description of quantum confinement effects which is crucial in these devices.
M3-level interconnect structure as imported from WP3 tools (Fraunhofer and GSS)
Example for nanowire devices used by CEA in SUPERAID7 (CEA)
M3-level interconnect structure: Electrostatic potential solution (GSS)
Electron density in ideal and rough wires (TU Wien)