Periodic Reporting for period 2 - SUPERAID7 (Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node)
Periodo di rendicontazione: 2017-07-01 al 2018-12-31
Among the physical limitations which challenge progress in nanoelectronics for aggressively scaled More Moore, process variability is getting ever more critical. Effects from various sources of process variations, both systematic and stochastic, influence each other and lead to variations of the electrical, thermal and mechanical behavior of devices, interconnects and circuits. Correlations are of key importance because they drastically affect the percentage of products which meet the specifications. Whereas the comprehensive experimental investigation of these effects is largely impossible, modelling and simulation (TCAD) offers the unique possibility to predefine process variations and trace their effects on subsequent process steps and on devices and circuits fabricated, just by changing the corresponding input data. This important requirement for and capability of simulation was among others highlighted in the International Technology Roadmap for Semiconductors ITRS.
SUPERAID7 has built upon the successful FP7 project SUPERTHEME (which focused on advanced More-than-Moore devices), and has established a software system for the simulation of the impact of systematic and statistical process variations on advanced More Moore devices and circuits down to the 7 nm node and below, including especially interconnects. This has needed improved physical models and extended compact models. Device architectures addressed in the benchmarks have included especially TriGate/ΩGate FETs and stacked nanowires, including alternative channel materials. The software developed was benchmarked utilizing background and sideground experiments of the partner CEA. Main channels for exploitation are software commercialization via the partner Synopsys and support of device architecture activities at CEA.
SUPERAID7 has built upon the successful FP7 project SUPERTHEME (which focused on advanced More-than-Moore devices), and has established a software system for the simulation of the impact of systematic and statistical process variations on advanced More Moore devices and circuits down to the 7 nm node and below, including especially interconnects. This has needed improved physical models and extended compact models. Device architectures addressed in the benchmarks have included especially TriGate/ΩGate FETs and stacked nanowires, including alternative channel materials. The software developed was benchmarked utilizing background and sideground experiments of the partner CEA. Main channels for exploitation are software commercialization via the partner Synopsys and support of device architecture activities at CEA.
In WP1 “Project Management” standard management actions were carried out.
In WP2 “Specifications and Benchmarks” specifications were defined for 7nm Trigate (FinFET) and 5nm Stacked-Nanowires MOSFET technology to be simulated. Morphological data and associated measured electrical characteristics for these devices were described in order to perform process and device simulation in WP3/WP4. The capability of the simulation tools to describe the morphological data and the electrical characteristics of Trigate and Gate-All-Around Stacked-Nanowires was assessed and demonstrated.
The work of WP3 “Variation-Aware Equipment and Process Simulation” was focused on the integration of the topography modules from Fraunhofer IISB and TU Wien (lithography, etching, deposition), both into a versatile topography simulation tool and with the Sentaurus environment, and on the development of physical models for topography steps. The latter was based on an analysis of the available capabilities of the modules and the resulting requirements for adaptations with respect to the SUPERAID7 benchmarks but also with respect to needs from the simulation end-user community as a whole.
In WP4 “Variation-Aware Device and Interconnect Simulation” a comprehensive strategy for the simulation of confined transport in nanowire transistors was developed and implemented. This included model and software development and the calibration and validation against data from literature. A fast field solver was developed to extract resistances and capacitances for advanced interconnect structures. This includes the capability to model global and statistical local variability due to line edge roughness and metal granularity.
In WP5 “Software Integration and Variation-Aware Compact Models” the topography simulation tools from Fraunhofer and TU Wien were integrated into the Sentaurus environment. A predictive and physical compact model (LETI-NSP) for Gate-All-Around stacked NanoWire/ NanoSheet MOSFET was developed by CEA-LETI. An improved TCAD-to-SPICE flow was developed through tight integration with Sentaurus Workbench and improved integration of Garand with other Sentaurus TCAD tools. The TCAD-to-SPICE tool flow was used to extract compact models that account for systematic and statistical variability and correlations.
Within WP6 “Dissemination” the SUPERAID7 WWW page was implemented and kept up-to-date. 40 papers on results from SUPERAID7 were published in Open Access so far, several presentations made at conferences and workshops, three workshops organized or co-organized, and the project presented at ENF 2016 and EFECS 2018.
First results from SUPERAID7 could already be commercialized. This includes especially the GSS/Synopsys integrated DTCO flow already made commercially available from Synopsys. Furthermore, the LETI-NSP compact model was introduced into international standardization via the compact model coalition (CMC) to allow for the inclusion in all major ECAD tools.
In WP2 “Specifications and Benchmarks” specifications were defined for 7nm Trigate (FinFET) and 5nm Stacked-Nanowires MOSFET technology to be simulated. Morphological data and associated measured electrical characteristics for these devices were described in order to perform process and device simulation in WP3/WP4. The capability of the simulation tools to describe the morphological data and the electrical characteristics of Trigate and Gate-All-Around Stacked-Nanowires was assessed and demonstrated.
The work of WP3 “Variation-Aware Equipment and Process Simulation” was focused on the integration of the topography modules from Fraunhofer IISB and TU Wien (lithography, etching, deposition), both into a versatile topography simulation tool and with the Sentaurus environment, and on the development of physical models for topography steps. The latter was based on an analysis of the available capabilities of the modules and the resulting requirements for adaptations with respect to the SUPERAID7 benchmarks but also with respect to needs from the simulation end-user community as a whole.
In WP4 “Variation-Aware Device and Interconnect Simulation” a comprehensive strategy for the simulation of confined transport in nanowire transistors was developed and implemented. This included model and software development and the calibration and validation against data from literature. A fast field solver was developed to extract resistances and capacitances for advanced interconnect structures. This includes the capability to model global and statistical local variability due to line edge roughness and metal granularity.
In WP5 “Software Integration and Variation-Aware Compact Models” the topography simulation tools from Fraunhofer and TU Wien were integrated into the Sentaurus environment. A predictive and physical compact model (LETI-NSP) for Gate-All-Around stacked NanoWire/ NanoSheet MOSFET was developed by CEA-LETI. An improved TCAD-to-SPICE flow was developed through tight integration with Sentaurus Workbench and improved integration of Garand with other Sentaurus TCAD tools. The TCAD-to-SPICE tool flow was used to extract compact models that account for systematic and statistical variability and correlations.
Within WP6 “Dissemination” the SUPERAID7 WWW page was implemented and kept up-to-date. 40 papers on results from SUPERAID7 were published in Open Access so far, several presentations made at conferences and workshops, three workshops organized or co-organized, and the project presented at ENF 2016 and EFECS 2018.
First results from SUPERAID7 could already be commercialized. This includes especially the GSS/Synopsys integrated DTCO flow already made commercially available from Synopsys. Furthermore, the LETI-NSP compact model was introduced into international standardization via the compact model coalition (CMC) to allow for the inclusion in all major ECAD tools.
In the following the progress and expected results are outlined for the four technical work packages WP2 to WP5.
The results obtained in WP2 summarize, for the first time, a very detailed database on morphological/electrical results of Trigate nanowire devices. For the first time, the Precession Electron Diffraction (PED) technique, with a nm-scale precision, was used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Advanced electrical characterization of these devices enabled us to calibrate a new physical compact model (LETI-NSP) in order to assess the performance of ring oscillators of GAA FETs.
In WP3, an integrated topography simulator was realized which, based on a unified Python frontend, seamlessly integrates the modules from Fraunhofer IISB and TUW for the simulation of lithography, etching, and deposition. The tool uses various levels of physical modeling for all steps involved. The possibility to run them in an integrated environment and to provide the structures to device and interconnect simulation is – to our knowledge – beyond state-of-the-art.
Within WP4 an advanced stochastic multi-subband device simulator based on a set of quantum confinement aware scattering models was developed. A quantum simulator accounting for source-to-drain tunneling which includes parameters obtained from first-principle (DFT) approaches and computes current and charge in mode space was successfully validated. The models and framework developed for interconnect simulation enable the investigation of the influence of surface roughness and grain boundary scattering on the electrical conductivity and electromigration-induced stress of copper nano-interconnects.
In WP5 a seamless integration of process simulation tools developed or extended within the project with the Sentaurus Workbench framework of Synopsys was achieved, which for the first time enabled the demonstration of impact of systematic variations of fundamental process steps, such as etching, deposition, and lithography. The LETI-NSP model has established itself as the first compact model for GAA stacked-Nanowire/Nanosheet MOSFET that can handle different cross-section shapes, different substrate orientations dependent mobility models, and quantum confinement effects, and has been validated and calibrated with experimental data. The Response-surface compact model extraction approach correctly captured the variations, and the circuit simulations performed with the extracted variability-aware compact models demonstrated how different process parameters can affect different aspects of the circuit behavior.
The results obtained in WP2 summarize, for the first time, a very detailed database on morphological/electrical results of Trigate nanowire devices. For the first time, the Precession Electron Diffraction (PED) technique, with a nm-scale precision, was used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Advanced electrical characterization of these devices enabled us to calibrate a new physical compact model (LETI-NSP) in order to assess the performance of ring oscillators of GAA FETs.
In WP3, an integrated topography simulator was realized which, based on a unified Python frontend, seamlessly integrates the modules from Fraunhofer IISB and TUW for the simulation of lithography, etching, and deposition. The tool uses various levels of physical modeling for all steps involved. The possibility to run them in an integrated environment and to provide the structures to device and interconnect simulation is – to our knowledge – beyond state-of-the-art.
Within WP4 an advanced stochastic multi-subband device simulator based on a set of quantum confinement aware scattering models was developed. A quantum simulator accounting for source-to-drain tunneling which includes parameters obtained from first-principle (DFT) approaches and computes current and charge in mode space was successfully validated. The models and framework developed for interconnect simulation enable the investigation of the influence of surface roughness and grain boundary scattering on the electrical conductivity and electromigration-induced stress of copper nano-interconnects.
In WP5 a seamless integration of process simulation tools developed or extended within the project with the Sentaurus Workbench framework of Synopsys was achieved, which for the first time enabled the demonstration of impact of systematic variations of fundamental process steps, such as etching, deposition, and lithography. The LETI-NSP model has established itself as the first compact model for GAA stacked-Nanowire/Nanosheet MOSFET that can handle different cross-section shapes, different substrate orientations dependent mobility models, and quantum confinement effects, and has been validated and calibrated with experimental data. The Response-surface compact model extraction approach correctly captured the variations, and the circuit simulations performed with the extracted variability-aware compact models demonstrated how different process parameters can affect different aspects of the circuit behavior.