In the following the progress and expected results are outlined for the four technical work packages WP2 to WP5.
The results obtained in WP2 summarize, for the first time, a very detailed database on morphological/electrical results of Trigate nanowire devices. For the first time, the Precession Electron Diffraction (PED) technique, with a nm-scale precision, was used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Advanced electrical characterization of these devices enabled us to calibrate a new physical compact model (LETI-NSP) in order to assess the performance of ring oscillators of GAA FETs.
In WP3, an integrated topography simulator was realized which, based on a unified Python frontend, seamlessly integrates the modules from Fraunhofer IISB and TUW for the simulation of lithography, etching, and deposition. The tool uses various levels of physical modeling for all steps involved. The possibility to run them in an integrated environment and to provide the structures to device and interconnect simulation is – to our knowledge – beyond state-of-the-art.
Within WP4 an advanced stochastic multi-subband device simulator based on a set of quantum confinement aware scattering models was developed. A quantum simulator accounting for source-to-drain tunneling which includes parameters obtained from first-principle (DFT) approaches and computes current and charge in mode space was successfully validated. The models and framework developed for interconnect simulation enable the investigation of the influence of surface roughness and grain boundary scattering on the electrical conductivity and electromigration-induced stress of copper nano-interconnects.
In WP5 a seamless integration of process simulation tools developed or extended within the project with the Sentaurus Workbench framework of Synopsys was achieved, which for the first time enabled the demonstration of impact of systematic variations of fundamental process steps, such as etching, deposition, and lithography. The LETI-NSP model has established itself as the first compact model for GAA stacked-Nanowire/Nanosheet MOSFET that can handle different cross-section shapes, different substrate orientations dependent mobility models, and quantum confinement effects, and has been validated and calibrated with experimental data. The Response-surface compact model extraction approach correctly captured the variations, and the circuit simulations performed with the extracted variability-aware compact models demonstrated how different process parameters can affect different aspects of the circuit behavior.
