Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node

Resultado final

Summary of results of SUPERAID7 dissemination actions (events, papers)
Hierarchical set of presentation foils and leaflets for use by SUPERAID7 partners and eventually by the EC services – to be updated until the end of the project
Publishable version of the Technology Implementation Plan

The Technology Implementatiion Plan will be prepared in two versions: A more detailed confidential one and a document with infomation selected for publication (this document)

Demonstration of correlation-aware simulation of impacts of statistical and systematic variability

Final version of SUPERAID7 WWW including restricted section and including material from the SUPERAID7 Workshop

Final version of SUPERAID7 WWW including restricted section (to be maintained at least three years beyond the project) and including material from the SUPERAID7 Workshop

Set-up of SUPERAID7 WWW including preliminary version of restricted section
Project Presentation

Public Project Presentation which will be made available especially at the public WWW page of SUPERAID7. Deliverable report to be also provided.

Public workshop on variability

A workshop on variability and its simulation will be organized towards the end of the project, in order to achieve best visibility of the overall project results.

Guide to research data disseminated from SUPERAID7

This document summarizes and links to research data generated within the SUPERAID7 project which could be disseminated without compromising confidentiality issues or commercial interest of partners. Experimental data used in SUPERAID7 could only be included to a limited extent, because it mainly resulted from background or sideground work of project or cooperation partners. Therefore, data included mainly refers to physical models developed, their comparison with literature or other models, generic benchmark studies or variability studies. The dissemination of these data is based on a hierarchical access principle. Here, this document serves as the entry point and guide in which an inventory of the data generated and disseminated is given, together with a link to the detailed data, which were in most cases published in journals or conference proceedings, and made available Open Access.

Publicaciones

Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5-nm CMOS Applications

Autores: Talib Al-Ameri, Vihar P. Georgiev, Fikru Adamu-Lema, Asen Asenov
Publicado en: IEEE Journal of the Electron Devices Society, Edición 5/6, 2017, Página(s) 466-472, ISSN 2168-6734
Editor: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/jeds.2017.2752465

Analysis of lense-governed Wigner signed particle quantum dynamics

Autores: Paul Ellinghaus, Josef Weinbub, Mihail Nedjalkov, Siegfried Selberherr
Publicado en: physica status solidi (RRL) - Rapid Research Letters, Edición 11/7, 2017, Página(s) 1700102, ISSN 1862-6254
Editor: Wiley - VCH Verlag GmbH & CO. KGaA
DOI: 10.1002/pssr.201700102

Experimental and Simulation Study of Silicon Nanowire Transistors Using Heavily Doped Channels

Autores: Vihar P. Georgiev, Muhammad M. Mirza, Alexandru-Iustin Dochioiu, Fikru Adamu-Lema, Salvatore M. Amoroso, Ewan Towie, Craig Riddet, Donald A. MacLaren, Asen Asenov, Douglas J. Paul
Publicado en: IEEE Transactions on Nanotechnology, Edición 16/5, 2017, Página(s) 727-735, ISSN 1536-125X
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tnano.2017.2665691

A Simple Interpolation Model for the Carrier Mobility in Trigate and Gate-All-Around Silicon NWFETs

Autores: Zaiping Zeng, Francois Triozon, Sylvain Barraud, Yann-Michel Niquet
Publicado en: IEEE Transactions on Electron Devices, Edición 64/6, 2017, Página(s) 2485-2491, ISSN 0018-9383
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2017.2691406

Correlation between the Golden Ratio and Nanowire Transistor Performance

Autores: Talib Al-Ameri
Publicado en: Applied Sciences, Edición 8/1, 2018, Página(s) 54, ISSN 2076-3417
Editor: MDPI
DOI: 10.3390/app8010054

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Autores: Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello
Publicado en: Solid-State Electronics, Edición 149, 2018, Página(s) 62-70, ISSN 0038-1101
Editor: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2018.08.012

Electrical characterization of vertically stacked p-FET SOI nanowires

Autores: Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello
Publicado en: Solid-State Electronics, Edición 141, 2018, Página(s) 84-91, ISSN 0038-1101
Editor: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2017.12.011

Variability Predictions for the Next Technology Generations of n-type SixGe1−x Nanowire MOSFETs

Autores: Jaehyun Lee, Oves Badami, Hamilton Carrillo-Nuñez, Salim Berrada, Cristina Medina-Bailon, Tapas Dutta, Fikru Adamu-Lema, Vihar Georgiev, Asen Asenov
Publicado en: Micromachines, Edición 9/12, 2018, Página(s) 643, ISSN 2072-666X
Editor: Multidisciplinary Digital Publishing Institute (MDPI)
DOI: 10.3390/mi9120643

Process Variability for Devices at and beyond the 7 nm Node

Autores: J. K. Lorenz, A. Asenov, E. Baer, S. Barraud, F. Kluepfel, C. Millar, M. Nedjalkov
Publicado en: ECS Journal of Solid State Science and Technology, Edición 7/11, 2018, Página(s) P595-P601, ISSN 2162-8769
Editor: Electrochemical Society, Inc.
DOI: 10.1149/2.0051811jss

(Invited) Process Variability for Devices at and Beyond the 7 nm Node

Autores: Juergen Klaus Lorenz, Asen Asenov, Eberhard Baer, Sylvain Barraud, Campbell Millar, Mihail Nedjalkov
Publicado en: ECS Transactions, Edición 85/8, 2018, Página(s) 113-124, ISSN 1938-5862
Editor: Electrochemical Society, Inc.
DOI: 10.1149/08508.0113ecst

Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review

Autores: Xaver Klemenschits, Siegfried Selberherr, Lado Filipovic
Publicado en: Micromachines, Edición 9/12, 2018, Página(s) 631, ISSN 2072-666X
Editor: Multidisciplinary Digital Publishing Institute (MDPI)
DOI: 10.3390/mi9120631

Stochastic analysis of surface roughness models in quantum wires

Autores: Mihail Nedjalkov, Paul Ellinghaus, Josef Weinbub, Toufik Sadi, Asen Asenov, Ivan Dimov, Siegfried Selberherr
Publicado en: Computer Physics Communications, Edición 228, 2018, Página(s) 30-37, ISSN 0010-4655
Editor: Elsevier BV
DOI: 10.1016/j.cpc.2018.03.010

Simulation of the Impact of Ionized Impurity Scattering on the Total Mobility in Si Nanowire Transistors

Autores: Toufik Sadi, Cristina Medina-Bailon, Mihail Nedjalkov, Jaehyun Lee, Oves Badami, Salim Berrada, Hamilton Carrillo-Nunez, Vihar Georgiev, Siegfried Selberherr, Asen Asenov
Publicado en: Materials, Edición 12/1, 2019, Página(s) 124, ISSN 1996-1944
Editor: MDPI Open Access Publishing
DOI: 10.3390/ma12010124

Process Variability—Technological Challenge and Design Issue for Nanoscale Devices

Autores: Jürgen Lorenz, Eberhard Bär, Sylvain Barraud, Andrew Brown, Peter Evanschitzky, Fabian Klüpfel, Liping Wang
Publicado en: Micromachines, Edición 10/1, 2019, Página(s) 6, ISSN 2072-666X
Editor: Multidisciplinary Digital Publishing Institute (MDPI)
DOI: 10.3390/mi10010006

Does a nanowire transistor follow the golden ratio? A 2D Poisson-Schrödinger/3D Monte Carlo simulation study

Autores: Talib Al-Ameri, V. P. Georgiev, Fikru Adamu-Lema, Asen Asenov
Publicado en: 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017, Página(s) 57-60, ISBN 978-4-86348-610-2
Editor: IEEE
DOI: 10.23919/sispad.2017.8085263

Stacked nanowires/nanosheets GAA MOSFET from technology to design enablement

Autores: J.-Ch. Barbe, S. Barraud, O. Rozeau, S. Martinia, J. Lacord, P. Blaise, Z. Zeng, L. Bourdet, F. Triozon, Y. Niquet
Publicado en: 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017, Página(s) 5-8, ISBN 978-4-86348-610-2
Editor: IEEE
DOI: 10.23919/sispad.2017.8085250

Performance and design considerations for gate-all-around stacked-NanoWires FETs

Autores: S. Barraud, V. Lapras, B. Previtali, M. P. Samson, J. Lacord, S. Martinie, M.-A. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J. M. Hartmann, C. Vizioz, C. Comboroure, F. Andrieu, J. C. Barbe, M. Vinet, T. Ernst
Publicado en: 2017 IEEE International Electron Devices Meeting (IEDM), 2017, Página(s) 29.2.1-29.2.4, ISBN 978-1-5386-3559-9
Editor: IEEE
DOI: 10.1109/iedm.2017.8268473

Stacked-Wires FETs for Advanced CMOS Scaling

Autores: S. Barraud, V. Lapras, M. Samson, B. Previtali, J. Hartmann, N. Rambal, C. Vizioz, V. Loup, C. Comboroure, F. Triozon, N. Bernier, D. Cooper, M. Vinet
Publicado en: Proceedings 2017 International Conference on Solid State Devices and Materials (SSDM 2017), 2017, Página(s) 1
Editor: 1

Wigner Analysis of Surface Roughness in Quantum Wires

Autores: Paul Ellinghaus, Mihail Nedjalkov, Josef Weinbub, Siegfried Selberherr
Publicado en: International Wigner Workshop (IW2), Book of Abstracts, 2017, Página(s) 40-41, ISBN 978-3-200-05129-4
Editor: Institute for Microelectronics, TU Wien, Austria

New method for individual electrical characterization of stacked SOI nanowire MOSFETs

Autores: Bruna Cardoso Paz, Mikael Casse, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello
Publicado en: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017, Página(s) 1-3, ISBN 978-1-5386-3766-1
Editor: IEEE
DOI: 10.1109/s3s.2017.8309237

Performance and transport analysis of vertically stacked p-FET SOI nanowires

Autores: Bruna Cardoso Paz, Marcelo Antonio Pavanello, Mikael Casse, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot
Publicado en: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Página(s) 79-82, ISBN 978-1-5090-5313-1
Editor: IEEE
DOI: 10.1109/ulis.2017.7962606

Modeling electromigration in nanoscaled copper interconnects

Autores: L. Filipovic, R.L. de Orio, W.H. Zisser, S. Selberherr
Publicado en: 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017, Página(s) 161-164, ISBN 978-4-86348-610-2
Editor: IEEE
DOI: 10.23919/sispad.2017.8085289

Wigner-signed Particles Study of Double Dopant Quantum Effects

Autores: Josef Weinbub, Mihail Nedjalkov, Ivan Dimov, Siegfried Selberherr
Publicado en: International Wigner Workshop (IW2), Book of Abstracts, 2017, Página(s) 50-51, ISBN 978-3-200-05129-4
Editor: Institute for Microelectronics, TU Wien, Austria

The Effect of Etching and Deposition Processes on the Width of Spacers Created during Self-Aligned Double Patterning

Autores: Eberhard Baer, Juergen Lorenz
Publicado en: 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018, Página(s) 236-239, ISBN 978-1-5386-6790-3
Editor: IEEE
DOI: 10.1109/sispad.2018.8551649

Quantum Transport Investigation of Threshold Voltage Variability in Sub-10 nm JunctionlessSi Nanowire FETs

Autores: Salim Berrada, Jaehyun Lee, Hamilton Carrillo-Nunez, Cristina Medina-Bailon, Fikru Adamu-Lema, Vihar Georgiev, Pr Asen Asenov
Publicado en: 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018, Página(s) 244-247, ISBN 978-1-5386-6790-3
Editor: IEEE
DOI: 10.1109/sispad.2018.8551638

Modeling of block copolymer dry etching for directed self-assembly lithography

Autores: Zelalem Tamrate Belete, Eberhard Baer, Andreas Erdmann
Publicado en: Advanced Etch Technology for Nanopatterning VII, 2018, Página(s) 28, ISBN 9781-510616714
Editor: SPIE
DOI: 10.1117/12.2299977

Unified feature scale model for etching in SF<inf>6</inf> and Cl plasma chemistries

Autores: Xaver Klemenschits, Siegfried Selberherr, Lado Filipovic
Publicado en: 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2018, Página(s) 1-4, ISBN 978-1-5386-4811-7
Editor: IEEE
DOI: 10.1109/ulis.2018.8354763

Modeling the Influence of Grains and Material Interfaces on Electromigration

Autores: Lado Filipovic, Roberto Lacerda de Orio
Publicado en: 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018, Página(s) 83-87, ISBN 978-1-5386-6790-3
Editor: IEEE
DOI: 10.1109/sispad.2018.8551746

The Impact of Dopant Diffusion on Random Dopant Fluctuation in Si Nanowire FETs: A Quantum Transport Study

Autores: Jaehyun Lee, Salim Berrada, Hamilton Carrillo-Nunez, Cristina Medina-Bailon, Fikru Adamu-Lema, Vihar P. Georgiev, Asen Asenov
Publicado en: 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018, Página(s) 280-283, ISBN 978-1-5386-6790-3
Editor: IEEE
DOI: 10.1109/sispad.2018.8551697

Study of the 1D Scattering Mechanisms' Impact on the Mobility in Si Nanowire Transistors

Autores: C. Medina-Bailon, T. Sadi, M. Nedjalkov, J. Lee, S. Berrada, H. Carrillo-Nunez, V. Georgiev, S. Selberherr, A. Asenov
Publicado en: 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2018, Página(s) 1-4, ISBN 978-1-5386-4811-7
Editor: IEEE
DOI: 10.1109/ulis.2018.8354723

Impact of the Effective Mass on the Mobility in Si Nanowire Transistors

Autores: Cristina Medina-Bailon, Toufik Sadi, Mihail Nedjalkov, Jaehyun Lee, Salim Berrada, Hamilton Carrillo-Nunez, Vihar P. Georgiev, Siegfried Selberherr, Asen Asenov
Publicado en: 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018, Página(s) 297-300, ISBN 978-1-5386-6790-3
Editor: IEEE
DOI: 10.1109/sispad.2018.8551630

High and low-field contact resistances in trigate devices in a Non-Equilibrium Green's Functions framework

Autores: Leo Bourdet, Jing Li, Johan Pelloux-Prayer, Francois Triozon, Mikael Casse, Sylvain Barraud, Sebastien Martinie, Denis Rideau, Yann-Michel Niquet
Publicado en: 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, Página(s) 291-294, ISBN 978-1-5090-0818-6
Editor: IEEE
DOI: 10.1109/SISPAD.2016.7605204

NSP: Physical compact model for stacked-planar and vertical Gate-All-Around MOSFETs

Autores: O. Rozeau, S. Martinie, T. Poiroux, F. Triozon, S. Barraud, J. Lacord, Y. M. Niquet, C. Tabone, R. Coquand, E. Augendre, M. Vinet, O. Faynot, J.-Ch. Barbe
Publicado en: 2016 IEEE International Electron Devices Meeting (IEDM), 2016, Página(s) 7.5.1-7.5.4, ISBN 978-1-5090-3902-9
Editor: IEEE
DOI: 10.1109/IEDM.2016.7838369

Impact of strain on the performance of Si nanowires transistors at the scaling limit: A 3D Monte Carlo/2D poisson schrodinger simulation study

Autores: Talib Al-Ameri, Vihar P. Georgiev, Fikru-Adamu Lema, Toufik Sadi, Xingsheng Wang, Ewan Towie, Craig Riddet, Craig Alexander, Asen Asenov
Publicado en: 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, Página(s) 213-216, ISBN 978-1-5090-0818-6
Editor: IEEE
DOI: 10.1109/SISPAD.2016.7605185

Size-dependent carrier mobilities in rectangular silicon nanowire devices

Autores: Zaiping Zeng, Francois Triozon, Yann-Michel Niquet, Sylvain Barraud
Publicado en: 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, Página(s) 257-260, ISBN 978-1-5090-0818-6
Editor: IEEE
DOI: 10.1109/SISPAD.2016.7605196

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

Autores: S. Barraud, V. Lapras, M.P. Samson, L. Gaben, L. Grenouillet, V. Maffini-Alvaro, Y. Morand, J. Daranlot, N. Rambal, B. Previtalli, S. Reboh, C. Tabone, R. Coquand, E. Augendre, O. Rozeau, J. M. Hartmann, C. Vizioz, C. Arvet, P. Pimenta-Barros, N. Posseme, V. Loup, C. Comboroure, C. Euvrard, V. Balan, I. Tinti, G. Audoit, N. Bernier, D. Cooper, Z. Saghi, F. Allain, A. Toffoli, O. Faynot, M. Vinet
Publicado en: 2016 IEEE International Electron Devices Meeting (IEDM), 2016, Página(s) 17.6.1-17.6.4, ISBN 978-1-5090-3902-9
Editor: IEEE
DOI: 10.1109/IEDM.2016.7838441

TCAD proven compact modelling re-centering technology for early 0.x PDKs

Autores: L. Wang, B. Cheng, P. Asenov, A. Pender, D. Reid, F. Adamu-Lema, C. Millar, A. Asenov
Publicado en: 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, Página(s) 157-160, ISBN 978-1-5090-0818-6
Editor: IEEE
DOI: 10.1109/SISPAD.2016.7605171

Carrier scattering by workfunction fluctuations and interface dipoles in high-K/metal gate stacks

Autores: Zaiping Zeng, Francois Triozon, Yann-Michel Niquet
Publicado en: 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, Página(s) 369-372, ISBN 978-1-5090-0818-6
Editor: IEEE
DOI: 10.1109/SISPAD.2016.7605223

One-dimensional multi-subband Monte Carlo simulation of charge transport in Si nanowire transistors

Autores: Toufik Sadi, Ewan Towie, Mihail Nedjalkov, Craig Riddet, Craig Alexander, Liping Wang, Vihar Georgiev, Andrew Brown, Campbell Millar, Asen Asenov
Publicado en: 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, Página(s) 23-26, ISBN 978-1-5090-0818-6
Editor: IEEE
DOI: 10.1109/SISPAD.2016.7605139

Experimental and simulation study of a high current 1D silicon nanowire transistor using heavily doped channels

Autores: Vihar P. Georgiev, Muhammad M. Mirza, Alexandru-Iustin Dochioiu, Fikru-Adamu Lema, Slavatore M. Amoroso, Ewan Towie, Craig Riddet, Donald A. MacLaren, Asen Asenov, Douglas J. Paul
Publicado en: 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), 2016, Página(s) 1-3, ISBN 978-1-5090-4352-1
Editor: IEEE
DOI: 10.1109/NMDC.2016.7777084

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