Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies

Periodic Reporting for period 2 - INSIGHT (Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies)

Reporting period: 2017-06-01 to 2019-05-31

There is a growing need for high-performance systems operating at millimeter wave frequencies, including radar sensors and high-capacity radio communication. Traditionally, III-V technology has been used thanks to the inherent advantageous transport properties of the III-V semiconductors, in spite of limited possibilities for mass production of integrated systems. The advanced processing technology and system integration for Si-based implementation offers an alternative solution, although at higher power consumption.

Within INSIGHT we use advanced epitaxial techniques to integrate III-V semiconductors on Si in the form of nanowires. These integrated III-V nanostructures are used as transistor channels in MOSFETs where the excellent electrostatic control of the nanowire geometry is used to drastically improve the transistor characterisitcs. In particular, the transistor RF-properties are characterized and used to design and implement demonstrator circuits in the millimeter wave frequency range.

During the project we have achieved a wide range of both technical accomplishments, scientific findings and impact in our research fields. Generally speaking, we have pushed the technology maturity of III-V MOSFET technology to the next level, achieving multiple world-records in DC performance. We have made significant breakthroughs in III-V device integration with Si technology, including 3D stacked hybrid Si-III-V circuits, and established CMOS-compatible epitaxy integration methods. We have taken GaSb-based pFET performance to the next level and demonstrated balanced performance in co-integrated vertical InAs nFET and GaSb pFETs. Finally, we have moved high-frequency performance of the INSIGHT technologies forward by great strides and in the end also demonstrated packaged InGaAs-on-Si LNA MMICs operating with 17 dB gain as high as at 250 GHz.

In conclusion, INSIGHT has been successful in a wide range of areas and has contributed greatly to making Europe the leaders in Si-integrated III-V MOSFET technology.

In the second half of the project the focus shifted towards the implementation of BEOL processes, circuit model development and design and realization of circuit elements with focus on the LNA. In addition, a strong effort was put on the GaSb p-MOSFET to bring its performance as high as possible. Furthermore, we executed an Industrial Roadshow in which representatives from the consortium has visited relevant Industry to disseminate the research results of the project.

Here follows an overview of key results of the project:

1) Pushing the boundaries of vertical nanowire MOSFET fabrication during the project by the incorporation of novel process modules including self-aligned source and drain, dielectric sidewall spacers, enabling gate lengths down to 20 nm and reduced parasitic capacitances. This has led to an improvement in Ion up to 400 µA/µm at 0.5 V, RF performance from fT/fmax = 50 GHz up to 150 GHz, with projected performance reaching fT/fmax = 475/590 GHz.

2) Development of planar III-V MOSHEMT low noise amplifiers on GaAs and silicon substrates with gate lengths down to 20 nm. The first III-V MOSHEMT amplifier on silicon substrates was demonstrated which exhibited an on-wafer measured gain of more than 17 dB between 220 and 280 GHz. First transistors on silicon with an extrinsic fT=200 GHz and fmax=640 GHz referenced to the RF interconnect level, which is relevant for the design of integrated analog RF circuits.

3) Hybrid Si/InGaAs RF CMOS circuit demonstration by collaboration between IBM, LETI and IAF. Using this 3D technology, Si CMOS inverters, InGaAs/Si CMOS inverters and InGaAs/Si 6T-SRAM circuits were successfully demonstrated for the first time.

4) A BCB-based BEOL platform applicable for III-V nanowire MOSFETs was successfully established, and implementation of a nanowire MOSFET technology design library including BEOL components and large signal models. This has led to circuit designs including fabricated LNAs at 60 GHz and 94 GHz as well as simulated PA, VCO, and mixer.

5) Successful co-integration of InGaAs and GaSb vertical nanowires obtained in the same growth run on a Si wafer. Extremely scaled nanowire diameters down to 10 nm and a self-aligned gate-last process resulted in balanced drive currents of 156 μA/μm and 98 μA/μm for the n-type and p-type co-integrated devices respectively. In addition, IBM demonstrated CMOS-compatible co-integration of InAs and GaSb lateral nanowires on a Si wafer by a two-step growth process.

6) Lateral III-V nanowire FETs on InP substrates with transconductance of gm > 3 mS/µm and with on-current of 650 µA/µm (at IOFF = 100 nA/µm and VDD = 0.5 V). This represents the highest ever reported on-current at VDD = 0.5 V for a transistor in any material system, including Si CMOS.

7) A novel InGaAs-drain heterostructure combined with a field-plate process improved the drain breakdown of vertical nanowire transistors, achieving breakdown at VDS = 4V, suitable for RF power amplifiers.

8) Established models for the effect of border traps on the RF performance, highlighting the effects due to dispersion in capacitance, conductances and trap losses.

9) Executed an Industrial Road Show, with visits to STM, Infineon and SOITECH. Also contributed to the IRDS and NEREID roadmaps.

The project has generated a high number of contributions to high-profile conferences and journals including IEDM, VLSI, Electron Device Letters and Nano Letters and even Nature Electronics (accepted). In most cases, performance well beyond state-of-the-art is demonstrated. The consortium has been very active contributors to the esteemed conferences IEDM and VLSI (in total 15 oral presentations), as well as the European Microwave Week and International Microwave Symposium. This is a receipt of the high level of impact the research results of INSIGHT have had on the research field.

Below follow some examples of areas where the project have results far beyond the state-of-the-art and where the potential impact is particularly high:

1. The novel and CMOS-compatible III-V on Si integration method (TASE) developed in INSIGHT has demonstrated excellent material properties, propelling III-V on Si device technology as a viable solution for monolithic high frequency applications.

2. The vertical nanowire device technology that has been evolved to a high-performing device process during the extent of INSIGHT provides a blueprint for the implementation of vertical transistors in future ultra-scaled nodes, even applicable to Si CMOS.

3. The monolithic hybrid III-V/Si circuit demonstrators developed within INSIGHT are front-runners in the research community's aim towards fully 3D integrated electronics, of high importance to the continued scaling of electronics in the next decade.

4. The DC device performance of many III-V nanowire devices in INSIGHT exhibits world-record performance, thus pushing the boundary for what is possible to do with MOSFET device technology.

5. An extensive set of models (oxide defects, large signal, small signal, circuit) provide a toolkit to predict accurately circuit performance and allow for efficient design of circuits in the developed technologies, which is highly important for their continued exploitation.

In summary, it is clear that INSIGHT has been successful in a wide range of areas and has contributed greatly to making Europe the leaders in Si-integrated III-V MOSFET technology.

insightd07ar01bp01zl-agnew1b.jpg

Periodic Reporting for period 2 - INSIGHT (Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies)

Share this page

Download