In the second half of the project the focus shifted towards the implementation of BEOL processes, circuit model development and design and realization of circuit elements with focus on the LNA. In addition, a strong effort was put on the GaSb p-MOSFET to bring its performance as high as possible. Furthermore, we executed an Industrial Roadshow in which representatives from the consortium has visited relevant Industry to disseminate the research results of the project.
Here follows an overview of key results of the project:
1) Pushing the boundaries of vertical nanowire MOSFET fabrication during the project by the incorporation of novel process modules including self-aligned source and drain, dielectric sidewall spacers, enabling gate lengths down to 20 nm and reduced parasitic capacitances. This has led to an improvement in Ion up to 400 µA/µm at 0.5 V, RF performance from fT/fmax = 50 GHz up to 150 GHz, with projected performance reaching fT/fmax = 475/590 GHz.
2) Development of planar III-V MOSHEMT low noise amplifiers on GaAs and silicon substrates with gate lengths down to 20 nm. The first III-V MOSHEMT amplifier on silicon substrates was demonstrated which exhibited an on-wafer measured gain of more than 17 dB between 220 and 280 GHz. First transistors on silicon with an extrinsic fT=200 GHz and fmax=640 GHz referenced to the RF interconnect level, which is relevant for the design of integrated analog RF circuits.
3) Hybrid Si/InGaAs RF CMOS circuit demonstration by collaboration between IBM, LETI and IAF. Using this 3D technology, Si CMOS inverters, InGaAs/Si CMOS inverters and InGaAs/Si 6T-SRAM circuits were successfully demonstrated for the first time.
4) A BCB-based BEOL platform applicable for III-V nanowire MOSFETs was successfully established, and implementation of a nanowire MOSFET technology design library including BEOL components and large signal models. This has led to circuit designs including fabricated LNAs at 60 GHz and 94 GHz as well as simulated PA, VCO, and mixer.
5) Successful co-integration of InGaAs and GaSb vertical nanowires obtained in the same growth run on a Si wafer. Extremely scaled nanowire diameters down to 10 nm and a self-aligned gate-last process resulted in balanced drive currents of 156 μA/μm and 98 μA/μm for the n-type and p-type co-integrated devices respectively. In addition, IBM demonstrated CMOS-compatible co-integration of InAs and GaSb lateral nanowires on a Si wafer by a two-step growth process.
6) Lateral III-V nanowire FETs on InP substrates with transconductance of gm > 3 mS/µm and with on-current of 650 µA/µm (at IOFF = 100 nA/µm and VDD = 0.5 V). This represents the highest ever reported on-current at VDD = 0.5 V for a transistor in any material system, including Si CMOS.
7) A novel InGaAs-drain heterostructure combined with a field-plate process improved the drain breakdown of vertical nanowire transistors, achieving breakdown at VDS = 4V, suitable for RF power amplifiers.
8) Established models for the effect of border traps on the RF performance, highlighting the effects due to dispersion in capacitance, conductances and trap losses.
9) Executed an Industrial Road Show, with visits to STM, Infineon and SOITECH. Also contributed to the IRDS and NEREID roadmaps.
