• What is the problem/issue being addressed?
CMOS transistor dimensions have been shrinking for decades in an almost regular manner. Nowadays this trend has reached a critical point and it is widely accepted that the trend will end in a decade. At this point, research is shifting to novel forms of nanotechnologies including selfassembled systems. Unlike conventional CMOS that can be patterned in complex ways with lithography, self-assembled nanoscale systems generally consist of regular structures. Logical functions and memory elements are achieved with arrays of crossbar-type switches. Here, the problem needed to be solved is “how to make efficient and high performance computing with nano arrays that includes logic synthesis, defect tolerance, and performance optimization?”, and it is the main motivation of this project.
• Why is it important for society?
The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New computing models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements both arithmetic and memory elements, necessitated by achieving a computer, by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of arithmetic and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of future and emerging computers beyond CMOS (current conventional computing technology).
• What are the overall objectives?
Research objectives:
The main objective of this project is developing a complete synthesis methodology for nanoscale switching crossbars that leads to the design and construction of an emerging computer. To achieve this objective, we follow a roadmap, with sub-objectives listed below.
First Research Objective: Finding optimal crossbar sizes, modelling, and optimization.
Second Research Objective: Implementing arithmetic and memory elements by considering reliability, area, delay, and power dissipation of the crossbars.
Third Research Objective: Realizing a nano-crossbar based synchronous state machine.
As the conclusion of the action, a complete synthesis methodology for nano-crossbar arrays that considers both technology specifics and performance metrics including reliability, area, delay, and power dissipation, has been achieved. It is shown that any computing device including a state machine can be implemented with the proposed methodology.
