Tail-PASS: Resource-based Cache Management for Tiled Graphics Rendering Hardware
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Autori:
Germán Ceballos, Erik Hagersten, David Black-Schaffer
Pubblicato in:
IEEE International Symposium on Parallel and Distributed Processing with Applications, 2018
Editore:
IEEE
DOI:
10.13140/RG.2.2.17919.25769
Freeway: Maximizing MLP for Slice-Out-of-Order Execution
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Autori:
Rakesh Kumar, Mehdi Alipour, David Black-Schaffer
Pubblicato in:
2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), Numero Washington, DC, 2019, Pagina/e 558-569, ISBN 978-1-7281-1444-6
Editore:
IEEE
DOI:
10.1109/hpca.2019.00009
Filter caching for free - the untapped potential of the store-buffer
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Autori:
Ricardo Alves, Alberto Ros, David Black-Schaffer, Stefanos Kaxiras
Pubblicato in:
Proceedings of the 46th International Symposium on Computer Architecture - ISCA '19, 2019, Pagina/e 436-448, ISBN 9781-450366694
Editore:
ACM Press
DOI:
10.1145/3307650.3322269
Efficient thread/page/parallelism autotuning for NUMA systems
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Autori:
Mihail Popov, Alexandra Jimborean, David Black-Schaffer
Pubblicato in:
Proceedings of the ACM International Conference on Supercomputing - ICS '19, 2019, Pagina/e 342-353, ISBN 9781-450360791
Editore:
ACM Press
DOI:
10.1145/3330345.3330376
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
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Autori:
Mehdi Alipour, Rakesh Kumar, Stefanos Kaxiras, David Black-Schaffer
Pubblicato in:
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Pagina/e 716-721, ISBN 978-3-9819263-2-3
Editore:
IEEE
DOI:
10.23919/date.2019.8715034
Perforated Pages: Supporting Fragmented Memory Allocation for Large Pages
Autori:
Chang Hyun Park, Sanghoon Cha, Bokyeong Kim, Youngjin Kwon, David Black-Schaffer, Jaehyuk Hu
Pubblicato in:
47th International Symposium on Computer Architecture, 2020
Editore:
IEEE
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors
Autori:
Mehdi Alipour, Rakesh Kumar, Stefanos Kaxiras, David Black-Schaffer
Pubblicato in:
26th IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2020
Editore:
IEEE
