The GaNonCMOS focus was first to define the system specifications for each of the different voltage regulator modules (VRM) demonstrators based on the complete set of application requirements. To achieve this, a study of the state of the art landscape was performed. This resulted in an extended list of demonstrators to build, including their required electrical specifications.
To develop a VRM system level model, this needs to have an optimized power conversion topology. The design of the GaN power switches, the magnetic components and the CMOS driver and control circuits was undertaken and finalized in a second stage.
At the materials level, new magnetic materials and deposition processes for application in high frequency magnetic cores were developed and tested. The epitaxial material to fabricate the GaN switches was successfully developed, fabricated and characterized.
The individual VRMs components were developed at all levels of integration. A functional embedded inductor demonstrator was manufactured and tested for a realistic application. Integrated thin-film Magnetics-on-Silicon (MoS) transformer devices were fabricated using a CMOS back-end-of-line (BEOL) compatible micro-fabrication process. A combined controller/driver IC was developed to adapt to the requirements of the different demonstrators including the chip-level demonstrator for direct wafer bonding. We developed high-power density DC-DC converters based on both monolithically integrated wire-bonded GaN switches and embedded GaN switches. The results suggested that the device design, the GaN epi-wafer quality, the device fabrication, and the converter design are suitable for the target applications. The packaging of the GaN chips using the embedding technology did not deteriorate the performance of the GaN devices.
We have run an ambitious PCB-demonstrator plan using materials, processes and technologies developed within the project, and with the goal of achieving very high-levels of miniaturization and packaging integration – as well be appropriate for next generation PoLs, iVRs and gate drivers systems in-package or on-chip. At chip-level, a combined BiCMOS and GaN wafer design, new planarization process for the BiCMOS line and an aligned direct wafer bonding process flow were developed.
The evaluation of the industrialization potential of the technology did not show real showstoppers on the manufacturability, supply chain and business models. The main challenge identified for the application of the technology is to get a good area match-up of CMOS and GaN to make the wafer-wafer bonding economically feasible.
The project also documented the business case, quantifying the value proposition of the GaNonCMOS technologies for the most promising markets (data centers and automotive). All partners compiled a list of key exploitable results, reporting first exploitation success stories such it is already the case for AT&S, TNIUCC and EpiGaN/SOITEC.
