Technology Advances and Key Enablers for Module Integration for 5 nm

Project Information

TAKEMI5

Grant agreement ID: 737479

DOI

10.3030/737479

Project closed

EC signature date 15 May 2017

Start date 1 April 2017

End date 30 November 2019

Funded under

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Total cost

€ 132 778 302,32

EU contribution

€ 28 339 999,24

Coordinated by

ASML NETHERLANDS B.V.
Netherlands

Periodic Reporting for period 2 - TAKEMI5 (Technology Advances and Key Enablers for Module Integration for 5 nm)

Reporting period: 2018-04-01 to 2019-11-30

Summary of the context and overall objectives of the project

In line with industry needs for the next generation Semiconductor technology for the manufacture of cost-effective high performance logic ICs – Moore’s Law - the main objective of the TAKEMI5 project is to discover, develop and demonstrate lithographic, metrology, process and integration technologies enabling module and device integration for the 5nm node.

In lithography EUV/NA0.33 scanners have been optimized for mix & match with existing DUV/NA1.35 scanners. For further IC scaling and cost reduction of the lithographic process the design of a new “Hyper NA” EUV has been completed and prepared for integrations.

In Metrology production ready metrology tools have been created for application in the 5nm node. The key challenges have been to improve resolution and enable multi-dimensional metrology capability for characterization and defect detection in “Under Layers”, that is beneath the surface of the chip.

In Process Development, Integration and Demonstration different process, module and device integration options have been explored to identify solution for devices that fulfil the performance, power, area and cost requirements of 5nm node technology.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

In Lithography scanner improvements and new alignment modules have been developed by ASML to improve matching between the DUV and EUV scanners. A cross platform matched machine overlay (XMMO) of 1.9nm has been demonstrated. which matches the requirements for the 5nm node. The Hyper NA EUV system design has been completed resulting in a full system design specification and integration plan.
For the realization of the Hyper NA EUV mirrors Zeiss developed numerous innovative techniques for mirror manufacture and evaluation. The first large mirror has been grinded and polished.
IMS in cooperation with Zeiss have defined the specification parameters and measurement techniques for the X-large Diffractive Optical Elements (DOE). A first evaluations has been carried out. And a manufacturing process has been developed and implemented resulting in homogeneous feature profiles that are independent of the position on the DOE substrate and its layout.

In metrology, the focus has been on the development of through layers mapping and multi-dimensional metrology capabilities by Applied Materials Israel, Nova, Semilab, KLA-Tencor Israel, FEI and TNO. The techniques involved are Scanning Electron Microscopy (SEM) defect review tool, Scanning Transmission Electron Microscopy (STEM), X-ray Photo-emission Spectroscopy (XPS), Optical dark field, Enhanced Raman and Scanning Probe Microscopy (SPM). In addition, productivity improvement, such as throughput and predictive analysis, were achieved on a system level, and across multiple systems, with high performance computing and the development of smart algorithms.
The main exploitations for the metrology work package members is the new ‘through layer mapping’ and ‘multi-dimensional metrology’ capabilities for key critical parameters, such as Critical Dimensions, Overlay and defects characterization, for the 5nm technology node.

In Process Development, Integration and Demonstration for 5nm technology node the patterning and advanced metallization options assessment consolidated in the demonstration of a three metal-level damascene BEOL integration, including electrical qualification, implementing a TiN liner / Ru bulk metal metallization scheme. Module development for tall FinFET, the target device for 5nm node, has been completed including the integration of Buried Power Rail and Self-Aligned Gate Contact scaling boosters. High-chi Block Co-Polymers (BCP) have been successfully assessed for resolving sub 20nm DSA lines/spaces, including reduction of the dislocation density with 7 orders of magnitude.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

Within the project all activities have been geared to move the capability of the industry to produce high performance logic ICs beyond the present state of the art, in fact enabling the Semiconductor Industry to migrate to the next technology node following Moore’s law.

In terms of societal implications the project results will enable development of new innovations in systems and services providing means to tackle the grand societal challenges such as Global warming and sustainable energy, Aging population, Sustainable food and water supply, Growing global population, Safety & Security and Connectivity & Digital Networks.

With the predominantly European based EUV Lithography equipment ecosystem, Europe can reinforce its lead in this part of the semiconductor equipment market. Moreover, the independent access to lithography technology for the manufacturing of Electronics Components and Systems (ECS) is indispensable for meeting the challenges of the European society, to increase sovereignty, and for being competitive with foreign market participants.

1nm accurate wafer stage from nanomotion