European Packaging, Assembly and Test Pilot for Manufacturing of Advanced System-in-Package

Información del proyecto

EuroPAT-MASIP

Identificador del acuerdo de subvención: 737497

DOI

10.3030/737497

Proyecto cerrado

Fecha de la firma de la CE 12 Mayo 2017

Fecha de inicio 1 Abril 2017

Fecha de finalización 30 Junio 2021

Financiado con arreglo a

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Coste total

€ 29 734 972,50

Aportación de la UE

€ 7 203 644,58

Coordinado por

ATEP - AMKOR TECHNOLOGY PORTUGAL SA
Portugal

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Resultado final

Documents, reports (1)

Project website

Other (1)

Communication tools

Project website, LinkedIn pages, visual code, reporting and powerpoint templates, newsletter platform and general presentation - brochures, roll-ups if need be

Publicaciones

Conference proceedings (10)

Chip package bumping on wafer level for RDL first Fan-Out wafer

Autores: Anshuma Pathak, Mathias Böttcher, Sebastiaan Kersjes, Thomas Oppert, Thorsten Teutsch
Publicado en: IMAPS Device Packaging 2021, 2021
Editor: IMAPS Device Packaging 2021

The Systematic Study of Fan-Out Wafer Warpage Using Analytical, Numerical and Experimental Methods

Autores: Ghanshyam Gadhiya, Sven Rzepka, Thomas Otto, Sebastiaan Kersjes, Felandorio Fernandes
Publicado en: ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, 2020, ISBN 978-0-7918-8404-1
Editor: American Society of Mechanical Engineers
DOI: 10.1115/ipack2020-2555

Virtual Prototyping, Design for Reliability, and Qualification for a Full SiP Product Portfolio of a FOWLP Line

Autores: Ghanshyam Gadhiya, Heikki Kuisma, Andre Cardoso, Birgit Bramer, Sven Rzepka, Thomas Otto
Publicado en: 2020 21st International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2020, Página(s) 1-8, ISBN 978-1-7281-6049-8
Editor: IEEE
DOI: 10.1109/eurosime48426.2020.9152629

FO-WLP multi-DOF inertial sensor for automotive applications

Autores: Heikki Kuisma, Andre Cardoso, Nikolai Mantyoja, Rudiger Rosenkrantz, Sami Nurmi, Martin Gall
Publicado en: 2018 7th Electronic System-Integration Technology Conference (ESTC), 2018, Página(s) 1-7, ISBN 978-1-5386-6814-6
Editor: IEEE
DOI: 10.1109/estc.2018.8546447

Laser Debonding Enabling Ultra-Thin Fan-Out WLP Devices

Autores: Thomas Uhrmann, Matthias Pichler, Julian Bravin, Daniel Burgstaller, Boris Povazay
Publicado en: 2018 7th Electronic System-Integration Technology Conference (ESTC), 2018, Página(s) 1-5, ISBN 978-1-5386-6814-6
Editor: IEEE
DOI: 10.1109/estc.2018.8546451

Automated Virtual Prototyping for Fastest Time-to-Market of New System in Package Solutions

Autores: Ghanshyam Gadhiya, Birgit Bramer, Sven Rzepka
Publicado en: 2018 7th Electronic System-Integration Technology Conference (ESTC), 2018, Página(s) 1-7, ISBN 978-1-5386-6814-6
Editor: IEEE
DOI: 10.1109/estc.2018.8546352

Defect-Free Dicing for Higher Device Reliability

Autores: Christopher Johnston, Fabien Piallat
Publicado en: 2018 7th Electronic System-Integration Technology Conference (ESTC), 2018, Página(s) 1-4, ISBN 978-1-5386-6814-6
Editor: IEEE
DOI: 10.1109/estc.2018.8546448

The Creation of a Validated Scheme for the Automated Optimization of Systems in Package Designs

Autores: Ghanshyam Gadhiya ; Birgit Braemer ; Sven Rzepka ; Thomas Otto
Publicado en: Smart Systems Integration; 13th International Conference and Exhibition on Integration Edicións of Miniaturized Systems, 2019, ISBN 978-3-8007-4919-5
Editor: VDE

Ultra-Thin QFN-Like 3D Package with 3D Integrated Passive Devices

Autores: Ayad Ghannam, Niek van Haare, Julian Bravin, Elisabeth Brandl, Birgit Brandstatter, Hannes Klingler, Benedikt Auer, Philippe Meunier, Sebastiaan Kersjes
Publicado en: 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, Página(s) 1789-1795, ISBN 978-1-7281-1499-6
Editor: IEEE
DOI: 10.1109/ectc.2019.00276

Assessment of FOWLP process dependent wafer warpage using parametric FE study

Autores: Ghanshyam Gadhiya, Birgit Bramer, Sven Rzepka, Thomas Otto
Publicado en: 2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC), 2019, Página(s) 1-8, ISBN 978-0-9568086-6-0
Editor: IEEE
DOI: 10.23919/empc44848.2019.8951805

Peer reviewed articles (1)

Determination of the Filler Distribution in an Epoxy Molding Compound Using High-Resolution X-Ray Computed Tomography

Autores: Emre Topal, Jurgen Gluch, Andre Clausner, Andre Cardoso, Ehrenfried Zschech
Publicado en: IEEE Transactions on Components, Packaging and Manufacturing Technology, Edición 11/3, 2021, Página(s) 504-509, ISSN 2156-3950
Editor: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/tcpmt.2020.3048672

Other (1)

Toward improved FOWLP manufacturing by using self-alignment process

Autores: Sabine Scherbaum ; Christof Landesberger ; Benedikt Auer ; Hannes Klingler ; Birgit Brandstaetter ; Elisabeth Brandl ; Julian Bravin
Publicado en: Smart Systems Integration; 13th International Conference and Exhibition on Integration Edicións of Miniaturized Systems, 2019, ISBN 978-3-8007-4919-5
Editor: VDE

Book chapters (1)

Handbook of Silicon Based MEMS Materials and Technologies3rd EditionChapter 33 - Fan-out wafer-level packaging as packaging technology for MEMS

Autores: Heikki Kuisma, André Cardoso and Tanja Braun
Publicado en: 2020, Página(s) Pages 707-720, ISBN 9780128177860
Editor: Elsevier

Derechos de propiedad intelectual

Patent (5)

PRESSURE SENSOR

Número de solicitud/publicación: 20 19050654
Fecha: 2019-09-12
Solicitante(s): TEKNOLOGIAN TUTKIMUSKESKUS VTT OY

ELECTRONIC SYSTEM AND METHOD FOR THE PRODUCTION OF AN ELECTRONIC SYSTEM USING A SACRIFICIAL MEMBER

Número de solicitud/publicación: 18 748941
Fecha: 2018-08-08
Solicitante(s): 3DIS TECHNOLOGIES

ELECTRONIC SYSTEM COMPRISING A LOWER REDISTRIBUTION LAYER AND METHOD FOR PRODUCING SUCH AN ELECTRONIC SYSTEM

Número de solicitud/publicación: 18 748943
Fecha: 2018-08-08
Solicitante(s): 3DIS TECHNOLOGIES

ELECTRICAL COMPONENT WITH INTERCONNECTION ELEMENTS

Número de solicitud/publicación: 20 20053342
Fecha: 2020-04-08
Solicitante(s): MURATA ELECTRONICS OY

METHOD FOR INTEGRATING AT LEAST ONE 3D INTERCONNECTION FOR THE MANUFACTURE OF AN INTEGRATED CIRCUIT

Número de solicitud/publicación: 16 770715
Fecha: 2016-09-14
Solicitante(s): 3DIS TECHNOLOGIES