European Packaging, Assembly and Test Pilot for Manufacturing of Advanced System-in-Package

Project Information

EuroPAT-MASIP

Grant agreement ID: 737497

DOI 10.3030/737497

Project closed

EC signature date 12 May 2017

Start date 1 April 2017

End date 30 June 2021

Funded under

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Total cost € 29 734 972,50

EU contribution € 7 203 644,58

Coordinated by

ATEP - AMKOR TECHNOLOGY PORTUGAL SA
Portugal

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Deliverables

Documents, reports (1)

Project website

Other (1)

Communication tools

Project website, LinkedIn pages, visual code, reporting and powerpoint templates, newsletter platform and general presentation - brochures, roll-ups if need be

Publications

Conference proceedings (10)

Chip package bumping on wafer level for RDL first Fan-Out wafer

Author(s): Anshuma Pathak, Mathias Böttcher, Sebastiaan Kersjes, Thomas Oppert, Thorsten Teutsch
Published in: IMAPS Device Packaging 2021, 2021
Publisher: IMAPS Device Packaging 2021

The Systematic Study of Fan-Out Wafer Warpage Using Analytical, Numerical and Experimental Methods

Author(s): Ghanshyam Gadhiya, Sven Rzepka, Thomas Otto, Sebastiaan Kersjes, Felandorio Fernandes
Published in: ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, 2020, ISBN 978-0-7918-8404-1
Publisher: American Society of Mechanical Engineers
DOI: 10.1115/ipack2020-2555

Virtual Prototyping, Design for Reliability, and Qualification for a Full SiP Product Portfolio of a FOWLP Line

Author(s): Ghanshyam Gadhiya, Heikki Kuisma, Andre Cardoso, Birgit Bramer, Sven Rzepka, Thomas Otto
Published in: 2020 21st International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2020, Page(s) 1-8, ISBN 978-1-7281-6049-8
Publisher: IEEE
DOI: 10.1109/eurosime48426.2020.9152629

FO-WLP multi-DOF inertial sensor for automotive applications

Author(s): Heikki Kuisma, Andre Cardoso, Nikolai Mantyoja, Rudiger Rosenkrantz, Sami Nurmi, Martin Gall
Published in: 2018 7th Electronic System-Integration Technology Conference (ESTC), 2018, Page(s) 1-7, ISBN 978-1-5386-6814-6
Publisher: IEEE
DOI: 10.1109/estc.2018.8546447

Laser Debonding Enabling Ultra-Thin Fan-Out WLP Devices

Author(s): Thomas Uhrmann, Matthias Pichler, Julian Bravin, Daniel Burgstaller, Boris Povazay
Published in: 2018 7th Electronic System-Integration Technology Conference (ESTC), 2018, Page(s) 1-5, ISBN 978-1-5386-6814-6
Publisher: IEEE
DOI: 10.1109/estc.2018.8546451

Automated Virtual Prototyping for Fastest Time-to-Market of New System in Package Solutions

Author(s): Ghanshyam Gadhiya, Birgit Bramer, Sven Rzepka
Published in: 2018 7th Electronic System-Integration Technology Conference (ESTC), 2018, Page(s) 1-7, ISBN 978-1-5386-6814-6
Publisher: IEEE
DOI: 10.1109/estc.2018.8546352

Defect-Free Dicing for Higher Device Reliability

Author(s): Christopher Johnston, Fabien Piallat
Published in: 2018 7th Electronic System-Integration Technology Conference (ESTC), 2018, Page(s) 1-4, ISBN 978-1-5386-6814-6
Publisher: IEEE
DOI: 10.1109/estc.2018.8546448

The Creation of a Validated Scheme for the Automated Optimization of Systems in Package Designs

Author(s): Ghanshyam Gadhiya ; Birgit Braemer ; Sven Rzepka ; Thomas Otto
Published in: Smart Systems Integration; 13th International Conference and Exhibition on Integration Issues of Miniaturized Systems, 2019, ISBN 978-3-8007-4919-5
Publisher: VDE

Ultra-Thin QFN-Like 3D Package with 3D Integrated Passive Devices

Author(s): Ayad Ghannam, Niek van Haare, Julian Bravin, Elisabeth Brandl, Birgit Brandstatter, Hannes Klingler, Benedikt Auer, Philippe Meunier, Sebastiaan Kersjes
Published in: 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, Page(s) 1789-1795, ISBN 978-1-7281-1499-6
Publisher: IEEE
DOI: 10.1109/ectc.2019.00276

Assessment of FOWLP process dependent wafer warpage using parametric FE study

Author(s): Ghanshyam Gadhiya, Birgit Bramer, Sven Rzepka, Thomas Otto
Published in: 2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC), 2019, Page(s) 1-8, ISBN 978-0-9568086-6-0
Publisher: IEEE
DOI: 10.23919/empc44848.2019.8951805

Peer reviewed articles (1)

Determination of the Filler Distribution in an Epoxy Molding Compound Using High-Resolution X-Ray Computed Tomography

Author(s): Emre Topal, Jurgen Gluch, Andre Clausner, Andre Cardoso, Ehrenfried Zschech
Published in: IEEE Transactions on Components, Packaging and Manufacturing Technology, Issue 11/3, 2021, Page(s) 504-509, ISSN 2156-3950
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/tcpmt.2020.3048672

Other (1)

Toward improved FOWLP manufacturing by using self-alignment process

Author(s): Sabine Scherbaum ; Christof Landesberger ; Benedikt Auer ; Hannes Klingler ; Birgit Brandstaetter ; Elisabeth Brandl ; Julian Bravin
Published in: Smart Systems Integration; 13th International Conference and Exhibition on Integration Issues of Miniaturized Systems, 2019, ISBN 978-3-8007-4919-5
Publisher: VDE

Book chapters (1)

Handbook of Silicon Based MEMS Materials and Technologies3rd EditionChapter 33 - Fan-out wafer-level packaging as packaging technology for MEMS

Author(s): Heikki Kuisma, André Cardoso and Tanja Braun
Published in: 2020, Page(s) Pages 707-720, ISBN 9780128177860
Publisher: Elsevier

Intellectual Property Rights

Patent (5)

ELECTRICAL COMPONENT WITH INTERCONNECTION ELEMENTS

Application/Publication number: 20 20053342
Date: 2020-04-08
Applicant(s): MURATA ELECTRONICS OY

PRESSURE SENSOR

Application/Publication number: 20 19050654
Date: 2019-09-12

ELECTRONIC SYSTEM COMPRISING A LOWER REDISTRIBUTION LAYER AND METHOD FOR PRODUCING SUCH AN ELECTRONIC SYSTEM

Application/Publication number: 18 748943
Date: 2018-08-08

ELECTRONIC SYSTEM AND METHOD FOR THE PRODUCTION OF AN ELECTRONIC SYSTEM USING A SACRIFICIAL MEMBER

Application/Publication number: 18 748941
Date: 2018-08-08

METHOD FOR INTEGRATING AT LEAST ONE 3D INTERCONNECTION FOR THE MANUFACTURE OF AN INTEGRATED CIRCUIT

Application/Publication number: 16 770715
Date: 2016-09-14