Mont-Blanc 2020, European scalable, modular and power efficient HPC processor

Resultado final

This report will be based on the Guidelines provided by the European Commission article 204 of the H2020 annotated Model Grant agreement and will include the following a final publishable summary of the work completed to date covering results the conclusions and socioeconomic impact of the project a chapter on awareness and wider societal implications as well as a report on the distribution of the Community financial contribution It will be presented in conjunction with the final report of Dissemination deliverable D25

Final report on dissemination activities

This report will summarize all the dissemination activities developed all along the projects duration including website and socialnetworks activity press releases publications patent applications presentations tutorials workshops etc

Set of (Mini) applications for HPC tests

This deliverable will specify a list of mini applications that exhibit the characteristic needs of all the segments targeted by MB2020 (e. g. HPC).

Summer school

Once finished the summer school addressed in sub-task sT2.2.2, we will elaborate a report including all the relevant information about this event (i.e., the number of attendants, the name and a short CV of the speakers, the presentations used in their talks and keynotes, etc.).

Publicaciones

"Mont-Blanc 2020: Simulation Efforts Towards Exascale High Performance Computing : Embedded Tutorial on ""DDECS-2020"""

Autores: Alejandro Nocua; Said Derradji; Gregory Vaumourin; Pierre-Axel Lagadec; Zoltan Menyhart
Publicado en: 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020, ISBN 978-1-7281-9938-2
Editor: IEEE
DOI: 10.1109/ddecs50862.2020.9095675

Performance Evaluation of ParalleX Execution model on Arm-based Platforms

Autores: Nikunj Gupta, Rohit Ashiwal, Bine Brank, Sateesh K. Peddoju, Dirk Pleiter
Publicado en: 2020 IEEE International Conference on Cluster Computing (CLUSTER), 2020, Página(s) 567-575, ISBN 978-1-7281-6677-3
Editor: IEEE
DOI: 10.1109/cluster49012.2020.00080

BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass

Autores: Iván Pérez; Enrique Vallejo; Miquel Moretó; Ramón Beivide
Publicado en: 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2020, ISBN 978-1-7281-4798-7
Editor: IEEE
DOI: 10.1109/ispass48437.2020.00015

Wavefront parallelization of recurrent neural networks on multi-core architectures

Autores: Robin Kumar Sharma, Marc Casas
Publicado en: Proceedings of the 34th ACM International Conference on Supercomputing, 2020, Página(s) 1-12, ISBN 9781450379830
Editor: ACM
DOI: 10.1145/3392717.3392762

Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors

Autores: Adria Armejach, Bine Brank, Jordi Cortina, François Dolique, Timothy Hayes, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem Lopez-Paradis, Laurent Marliac, Miquel Moreto, Pedro Marcuello, Dirk Pleiter, Xubin Tan, Said Derradji
Publicado en: DATE 2021 Proceedings, 2021
Editor: IEEE

Porting Applications to Arm-based Processors

Autores: Bine Brank, Stepan Nassyr, Fatemeh Pouyan, Dirk Pleiter
Publicado en: 2020 IEEE International Conference on Cluster Computing (CLUSTER), 2020, Página(s) 559-566, ISBN 978-1-7281-6677-3
Editor: IEEE
DOI: 10.1109/cluster49012.2020.00079

TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism

Autores: Kallia Chronaki, Marc Casas, Miquel Moreto, Jaume Bosch, Rosa M. Badia
Publicado en: ISC 2018 Proceedings, 2018, Página(s) 389-409
Editor: Springer International Publishing
DOI: 10.1007/978-3-319-92040-5_20

Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs

Autores: Lluc Alvarez, Marc Casas, Jesus Labarta, Eduard Ayguade, Mateo Valero, Miquel Moreto
Publicado en: Proceedings of the 2018 International Conference on Supercomputing - ICS '18, 2018, Página(s) 218-228, ISBN 9781-450357838
Editor: ACM Press
DOI: 10.1145/3205289.3205312

Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies

Autores: Isaac Sánchez Barrera, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas
Publicado en: Proceedings of the 2018 International Conference on Supercomputing - ICS '18, 2018, Página(s) 207-217, ISBN 9781-450357838
Editor: ACM Press
DOI: 10.1145/3205289.3205310

Runtime-Assisted Cache Coherence Deactivation in Task Parallel Programs

Autores: Paul Caheny, Lluc Alvarez, Mateo Valero, Miquel Moreto, Marc Casas
Publicado en: SC18: International Conference for High Performance Computing, Networking, Storage and Analysis, 2018, Página(s) 454-465, ISBN 978-1-5386-8384-2
Editor: IEEE
DOI: 10.1109/sc.2018.00038

Stencil codes on a vector length agnostic architecture

Autores: Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó
Publicado en: Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques - PACT '18, 2018, Página(s) 1-12, ISBN 9781-450359863
Editor: ACM Press
DOI: 10.1145/3243176.3243192

Teaching HPC Systems and Parallel Programming with Small-Scale Clusters

Autores: Lluc Alvarez, Eduard Ayguade, Filippo Mantovani
Publicado en: 2018 IEEE/ACM Workshop on Education for High-Performance Computing (EduHPC), 2018, Página(s) 1-10, ISBN 978-1-7281-0190-3
Editor: IEEE
DOI: 10.1109/EduHPC.2018.00004

Enabling HPC Applications for SVE

Autores: Pleiter, Dirk; Brank, Bine; Ho, Nam; Nassyr, Stepan; Portero, Antonio
Publicado en: Arm Research Summit 2019, Austin, USA, 2019-09-15 - 2019-09-18, Edición 1, 2019
Editor: Arm Research Summit

A Vulnerability Factor for ECC-protected Memory

Autores: Luc Jaulmes, Miquel Moreto, Mateo Valero, Marc Casas
Publicado en: 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Página(s) 176-181, ISBN 978-1-7281-2490-2
Editor: IEEE
DOI: 10.1109/IOLTS.2019.8854397

Mont-Blanc 2020 NoC: A low-power and high bandwidth Network on Chip generator

Autores: Pierre-Axel Lagadec, Saïd Derradji, Alejandro Nocua, Zoltan Menyhart
Publicado en: Proceedings of the 3rd International Conference on Microelectronic Devices and Technologies (MicDAT '2020), Edición October 2020, 2020, Página(s) 18-22
Editor: International Frequency Sensor Association (IFSA) Publishing, S. L

The gem5 Simulator: Version 20.0+

Autores: Lowe-Power, Jason; Ahmad, Abdul Mutaal; Akram, Ayaz; Alian, Mohammad; Amslinger, Rico; Andreozzi, Matteo; Armejach, Adrià; Asmussen, Nils; Bharadwaj, Srikant; Black, Gabe; Bloom, Gedare; Bruce, Bobby R.; Carvalho, Daniel Rodrigues; Castrillon, Jeronimo; Chen, Lizhong; Derumigny, Nicolas; Diestelhorst, Stephan; Elsasser, Wendy; Fariborz, Marjan; Farmahini-Farahani, Amin; Fotouhi, Pouya; Gambord, R
Publicado en: Edición 1, 2020
Editor: Arxiv

Using Arm’s scalable vector extension on stencil codes

Autores: Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó
Publicado en: The Journal of Supercomputing, Edición 76/3, 2020, Página(s) 2039-2062, ISSN 0920-8542
Editor: Kluwer Academic Publishers
DOI: 10.1007/s11227-019-02842-5

On the maturity of parallel applications for asymmetric multi-core processors

Autores: Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Mateo Valero
Publicado en: Journal of Parallel and Distributed Computing, Edición 127, 2019, Página(s) 105-115, ISSN 0743-7315
Editor: Academic Press
DOI: 10.1016/j.jpdc.2019.01.007

Checkpoint/restart approaches for a thread-based MPI runtime

Autores: Julien Adam, Maxime Kermarquer, Jean-Baptiste Besnard, Leonardo Bautista-Gomez, Marc Pérache, Patrick Carribault, Julien Jaeger, Allen D. Malony, Sameer Shende
Publicado en: Parallel Computing, Edición 85, 2019, Página(s) 204-219, ISSN 0167-8191
Editor: Elsevier BV
DOI: 10.1016/j.parco.2019.02.006

Design trade-offs for emerging HPC processors based on mobile market technology

Autores: Adrià Armejach, Marc Casas, Miquel Moretó
Publicado en: The Journal of Supercomputing, Edición 75/9, 2019, Página(s) 5717-5740, ISSN 0920-8542
Editor: Kluwer Academic Publishers
DOI: 10.1007/s11227-019-02819-4

Memory Vulnerability: A Case for Delaying Error Reporting

Autores: Jaulmes, Luc; Moretó, Miquel; Valero, Mateo; Casas, Marc
Publicado en: Edición 1, 2018
Editor: Cornel University

On the Benefits of Tasking with OpenMP

Autores: Alejandro Rico, Isaac Sánchez Barrera, Jose A. Joao, Joshua Randall, Marc Casas, Miquel Moretó
Publicado en: OpenMP: Conquering the Full Hardware Spectrum - 15th International Workshop on OpenMP, IWOMP 2019, Auckland, New Zealand, September 11–13, 2019, Proceedings, Edición 11718, 2019, Página(s) 217-230, ISBN 978-3-030-28595-1
Editor: Springer International Publishing
DOI: 10.1007/978-3-030-28596-8_15

Derechos de propiedad intelectual

Procédé d'accélération de l'exécution d'un programme à chemin unique par exécution en parallèle de séquences conditionnellement concurrente

Número de solicitud/publicación: PCT/FR2019 051768
Fecha: 2018-07-18

Procédé d'accélération de l'exécution d'un programme à chemin unique par exécution en parallèle de séquences conditionnellement concurrente

Número de solicitud/publicación: PCT/FR2019 051768
Fecha: 2018-07-18

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Resultado final

Publicaciones

Derechos de propiedad intelectual

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