Descripción del proyecto
Los procesadores nacionales marcarán el comienzo de los superordenadores europeos a exaescala
Reforzar la capacidad industrial europea en el diseño de procesadores contribuirá al desarrollo del procesador del mañana para superordenadores a exaescala. El proyecto Mont-Blanc 2020, financiado con fondos europeos, tiene como objetivo crear un procesador de bajo consumo capaz de gestionar cargas de trabajo de informática de alto rendimiento (HPC, por sus siglas en inglés) y servidores. El procesador será más versátil, fiable y seguro, al tiempo que ofrecerá un mejor rendimiento general. Para hacerlo realidad, el equipo del proyecto desarrollará una metodología de codiseño para verificar y optimizar la infraestructura del sistema en chip, introducir avances que mejoren la eficiencia de las aplicaciones reales y obtener una ventaja competitiva. Además, el proyecto construirá IP para un procesador HPC.
Objetivo
The Mont-Blanc 2020 (MB2020) project ambitions to initiate the development of a future low-power European processor for Exascale. MB2020 lays the foundation for a European consortium aiming at delivering a processor with great energy efficiency for HPC and server workloads. A first generation product is scheduled in the 2020 time frame.
Our target is to reach exascale-level power efficiency (50 Gflops/Watt at processor level) with a second generation planned for 2022. Therefore, we will, within MB2020:
1. define a low-power System-on-Chip (SoC) implementation targeting Exascale, with built-in security and reliability features;
2. introduce strong innovations to improve efficiency with real-life applications and to outperform competition (vector instruction implementation, memory latency and bandwidth, power management, 2.5D integration);
3. develop key modules (IPs) needed for this implementation;
4. provide a working prototype demonstrating MB2020 key components and system level simulations, with a co-design approach based on real-life applications;
5. explore the reuse of these building blocks to serve other markets than HPC.
Our key choices are:
a) To use the ARM ISA (Instruction Set Architecture) because its has strong technological relevance and it offers a dynamic ecosystem, which is needed to deliver the system software and applications mandatory for successful market acceptance.
b) To design, implement or leverage new technologies (Scalable Vector Extension, NoC, High Bandwidth Memory, Power Management, …) as well as innovative packaging technologies to improve the versatility, performance, power efficiency, reliability, and security of the processor.
c) To improve on the economic sustainability of processor development through a modular design that allows to retarget our SoC for different markets.
Ámbito científico
- engineering and technologymechanical engineeringvehicle engineeringautomotive engineeringautonomous vehicles
- natural sciencescomputer and information sciencessoftwaresoftware applicationssystem software
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringroboticsautonomous robotsdrones
- natural sciencesbiological sciencesecologyecosystems
- social scienceseconomics and businessbusiness and managementemployment
Programa(s)
Tema(s)
Convocatoria de propuestas
Consulte otros proyectos de esta convocatoriaConvocatoria de subcontratación
H2020-ICT-2017-1
Régimen de financiación
RIA - Research and Innovation actionCoordinador
78340 Les Clayes Sous Bois
Francia