Skip to main content

High Performance and High Yield Heterogeneous III-V/Si Photonic Integrated Circuits using a Thin and Uniform Bonding Layer

Periodic Reporting for period 1 - PICTURE (High Performance and High Yield Heterogeneous III-V/Si Photonic Integrated Circuits using a Thin and Uniform Bonding Layer)

Reporting period: 2018-01-01 to 2019-06-30

The data rate of the signals being transported in today’s networks is increasing at a steady pace, mainly due to the booming communication needs. Transporting such an amount of data with existing technologies will soon reach major limits, in terms of power consumption, device density and weight of the network key subsystems. A way to push such limits is the utilization of photonic integrated circuits (PIC), which are aimed to reduce power consumption, size and cost of network equipment’s. The reduction of power consumption is mainly due to the use of a common Thermal Electrical Cooler for all the components integrated on a same circuit, provided a smart thermal management is designed and implemented. The size reduction comes from the integration of many devices on a same chipset and from the utilization of integrated waveguides for interconnection. A single packaging instead of individual component packaging results in cost reduction (and all components are fabricated on the same wafer).
Today 2 photonic integration platforms coexist: III-V on InP substrates and silicon. InP integration platform allows to produce high performance active photonic components such as laser, modulator and photodetector. It has made tremendous progress since a decade. Silicon photonics can take advantage of mature fabrication tools and processes that have been developed for EICs. The cost of silicon PICs can be favorably compared with that of InP-based: wafers with diameters of 200 mm and 300 mm being the standard for silicon PICs, while InP’s use 100 mm or smaller wafers. The number of individual PIC chips per silicon wafer is of a factor 4 or 9 compared to its InP counterpart.
Silicon photonics is now considered as a reliable photonic integration platform. It can address a wide range of applications from short-distance data communication to long-haul optical transmission. However, practical Si-based light sources are still missing. This situation has propelled research on heterogeneous integration of III-V semiconductors with silicon via wafer bonding techniques. In this approach, unstructured InP dies or wafers are bonded to an SOI waveguide circuit wafer. The InP substrate is removed and the III-V epitaxial film is processed.
It turns out that the heterogeneous integration of III-V on silicon allows more functionalities than just the laser sources and photodiodes: wavelength tunable laser for example. III-V dies allow the laser operation, while the n-doped InP and p-doped silicon layers, with a dielectric layer in between form a metal-oxide-semiconductor (MOS) capacitor. Hybrid III-V/Si MOS capacitive (MOSCAP) modulators can take advantage of the same physical mechanisms. Low drive voltage and low losses can be achieved by using a thin dielectric layer and by optimizing the composition of the III-V materials.
The development of a thin bonding oxide in 200mm was successfully achieved by CEA-Leti. It required the fabrication of complex silicon photonic circuits. The quality of the bonding oxide was qualified through wafer bonding of 200-mm SOI wafer and die bonding of III-V substrates.
A new MOVPE reactor has been installed at III-V Lab at the beginning of the project. Qualification and calibration campaigns have been carried out in order to control key parameters for the growth of inverted laser structures. High crystalline quality of III-V has been achieved onto 3-inch wafers for C-band lasers (6 in-spec wfers). The same laser structure was grown onto 2-inch wafers. The control of growth conditions allowed to deliver a new batch of nine C-band laser structures onto 3-inch wafers. O-band laser/modulator and photodiode stacks were successfully developed for die bonding.
The fabrication of the 1st mask set ‘’PIC-A’’ on 200 mm wafers flow involved 11 levels using both 248nm and 193nm DUV lithography, as well as e-beam lithography. An unprecedented process flow was specifically developed for the patterning of the two faces of SOI wafers by CEA-Leti.
Both hybrid III-V/Si MOSCAP modulator-based PIC design and Si-based capacitive modulator designs have been achieved by III-V Lab and Southampton University respectively.
A first-generation hybrid III-V/Si building blocks was designed including SOAs, lasers, photodiodes, and MOSCAP modulators by III-V Lab. Demonstration PICs have been implemented on the same mask layout, taking into account the packaging constraints (Argotech and Tyndall). SOI fabrication being achieved, the III-V mask layouts are ready for backend processing.
As for Si-based capacitive modulators, 30Gb/s operation has been demonstrated and a new design was achieved. Fabrication is under way. An effort was made in this new design, to make the Silicon MOSCAP modulators compatible with packaging, mitigating the risk of delivery of hybrid III-V/Si PIC and ensures PIC chipset delivery for demo PIC packaging.
2nd generation demo PICs are also designed taking into account the flip-chipping of the EIC and the new packaging constraints including QD lasers (DFB and FP lasers) and SAG DFB lasers /modulators both grown on templates.
The growth of InP/InGaAs on 4-inch InP substrate was investigated by AFM and met the roughness specification for bonding in terms at III-V Lab: bonding process was successful.
The regrowth of MQW on InP-on-SOI was done and were compared to reference on InP. The III-V heterostructure was characterized by XRD, PL and AFM.
The growth and optimization of high-density InAs QDs with high photoluminescence intensity (essential for DFB lasers) has been achieved by UCL. Under optimal growth conditions, high-quality InAs/GaAs QDs have been demonstrated with a density of 5E10 cm-2, strong RT-PL and a narrow linewidth of <30 meV. Initial laser results are very promising.
SAG masks design has been carried out for the InP on SOI templates. A fabrication process has been developed for dielectric masks. Templates were successfully patterned, enabling a wavelength emission range > 100 nm.
Report on the specifications of the building blocks and the complete PICs has been delivered by Nokia-Bell Labs. Mask layout for the 1st run SOI was delivered and fabrication of PIC-A SOI and III-V wafer deliveries were carried out. Mask layout for III-V back end processing was also achieved. This 1st run layout contains demonstration PICs. 2nd generation PICs are being designed, compatible with EIC flip-chipping.
The design specifications for the 60GBd TIA and driver has been defined. 1st generation TIA and driver test samples are available and have been delivered for assembly assessment. 2nd generation TIA has been designed and successfully taped-out.
Design rules for the PICs have been completed allowing the completion of the layouts. A packaging concept has been completed including the electrical, optical, thermal and mechanical interfaces for the PICs from the first run. The thermal management and the optical interface have been designed by Imec and Argotech.
Specifications in terms of optical budget and bandwidth requirements to achieve two 400 Gbps PICs for both direct-detection and coherent-detection based transmission systems were defined and summarized in a report. The testbed including large-bandwidth digital-to-analog and analog-to-digital converters (DAC/ADCs) for data generation and acquisition was validated using state-of-the-art optical transmitters and receivers, ready for the performance evaluation of the foreseen PICs.