Periodic Reporting for period 2 - PICTURE (High Performance and High Yield Heterogeneous III-V/Si Photonic Integrated Circuits using a Thin and Uniform Bonding Layer)
Période du rapport: 2019-07-01 au 2020-12-31
The data rate of the signals being transported in today’s networks is increasing at a steady pace, due to the booming communication needs. Transporting data with existing technologies will soon reach major limits, in terms of power consumption, device density and weight of the network key subsystems. A way to push such limits is the utilization of photonic integrated circuits (PIC), with the objective to reduce power consumption, size and cost of network equipment’s. The reduction of power consumption can be achieved through the use of a common Thermal Electrical Cooler for all the components integrated on a same circuit, provided a smart thermal management is designed and implemented. The size reduction comes from the integration of devices on a same chipset and the use of integrated waveguides for interconnection. A single packaging instead of individual component will result in cost reduction (all components being fabricated on the same wafer).2 photonic integration platforms coexist: III-V on InP substrates and silicon. InP integration platform allows to produce high performance active photonic components such as laser, modulator and photodetector. Silicon photonics can take advantage of mature fabrication tools and processes developed for EICs. The cost of silicon PICs can be favorably compared with that of InP-based: wafers with diameters of 200 mm and 300 mm being the standard for silicon PICs, while InP is limited to 100 mm wafers. The number of individual PIC chips per silicon wafer is of a factor 4 or 9 compared to its InP counterpart. Silicon photonics is now considered as a reliable photonic integration platform. It can address a wide range of applications from short-distance datacom to long-haul optical transmission. However, practical Si-based light sources are still missing. This situation has propelled research on heterogeneous integration of III-V semiconductors with silicon via wafer bonding techniques. In this approach, InP dies or wafers are bonded to an SOI waveguide circuit wafer. The InP substrate is then removed and the III-V film processed. The heterogeneous integration of III-V on Si allows more functionalities than just the laser sources and photodiodes: wavelength tunable laser for example. III-V dies allow laser operation, while n-doped InP and p-doped silicon layers, with a dielectric layer in between form a metal-oxide-semiconductor (MOS) capacitor. Hybrid III-V/Si MOS capacitive (MOSCAP) modulators can take advantage of the same physical mechanisms. Low drive voltage and low losses can be achieved by using a thin dielectric layer and by optimizing the composition of the III-V material.
The development of a thin bonding oxide was successfully achieved. It required the fabrication of complex silicon photonic circuits. The quality of the bonding oxide was qualified through wafer bonding of 200-mm SOI wafer and die bonding of III-V substrates. High crystalline quality of III-V material has been achieved for C-band lasers, O-band laser, modulator and photodiode stacks were successfully developed for die bonding. The fabrication of the 1st mask set on 200 mm wafers flow involved 11 levels using DUV lithography, as well as e-beam lithography. An unprecedented process flow was specifically developed for the patterning of the two sides of SOI wafers.
Both hybrid III-V/Si MOSCAP modulator-based PIC design and Si-based capacitive modulator designs have been achieved. A first-generation hybrid III-V/Si building blocks was designed including SOAs, lasers, photodiodes, and MOSCAP modulators. Demonstration PICs have been implemented on the same mask layout, taking into account the packaging constraints. As for Si-based capacitive modulators, 30Gb/s operation has been demonstrated and a new design was achieved. The Silicon MOSCAP modulators are compatible with packaging, mitigating difficulties related to hybrid III-V/Si MOSCAP hence ensuring PIC chipset delivery for PIC packaging. 2nd generation PICs are designed taking into account the flip-chipping of the EIC and the new packaging constraints including QD lasers (DFB and FP lasers) and SAG DFB lasers /modulators both grown on templates.The regrowth of MQW on InP-on-SOI was done and were compared to reference on InP. The growth and optimization of high-density InAs QDs with high photoluminescence intensity has been achieved. High-quality InAs/GaAs QDs have been demonstrated with a density of 5E10 cm-2, strong RT-PL and a narrow linewidth of <30 meV with promising initial laser results. SAG masks design has been carried out for InP on SOI templates. Fabrication process has been developed for dielectric masks. Templates were successfully patterned, enabling a wavelength emission range > 100 nm. Report on the specifications of the building blocks and the complete PICs has been delivered. Mask layout for the 1st run SOI was delivered and fabrication of PIC SOI and III-V wafer deliveries were carried out. Mask layout for III-V back end processing was also achieved. This 1st run layout contains demonstration PICs. 2nd generation PICs designed are compatible with EIC flip-chipping. The design specifications for the 60GBd TIA and driver has been defined. 1st generation TIA and driver test samples have been delivered for assembly. 2nd generation TIA has been designed and successfully taped-out. Design rules for the PICs have been completed allowing completion of the layouts. Packaging concept has been completed including the electrical, optical, thermal and mechanical interfaces for the PICs. Specifications in terms of optical budget and bandwidth requirements to achieve two 400 Gbps PICs for both direct-detection and coherent-detection based transmission systems were defined and summarized in a report. The testbed includes large-bandwidth digital-to-analog and analog-to-digital converters (DAC/ADC) for data generation and acquisition using state-of-the-art optical transmitters and receivers, ready for the performance evaluation of the foreseen PICs.
Both hybrid III-V/Si MOSCAP modulator-based PIC design and Si-based capacitive modulator designs have been achieved. A first-generation hybrid III-V/Si building blocks was designed including SOAs, lasers, photodiodes, and MOSCAP modulators. Demonstration PICs have been implemented on the same mask layout, taking into account the packaging constraints. As for Si-based capacitive modulators, 30Gb/s operation has been demonstrated and a new design was achieved. The Silicon MOSCAP modulators are compatible with packaging, mitigating difficulties related to hybrid III-V/Si MOSCAP hence ensuring PIC chipset delivery for PIC packaging. 2nd generation PICs are designed taking into account the flip-chipping of the EIC and the new packaging constraints including QD lasers (DFB and FP lasers) and SAG DFB lasers /modulators both grown on templates.The regrowth of MQW on InP-on-SOI was done and were compared to reference on InP. The growth and optimization of high-density InAs QDs with high photoluminescence intensity has been achieved. High-quality InAs/GaAs QDs have been demonstrated with a density of 5E10 cm-2, strong RT-PL and a narrow linewidth of <30 meV with promising initial laser results. SAG masks design has been carried out for InP on SOI templates. Fabrication process has been developed for dielectric masks. Templates were successfully patterned, enabling a wavelength emission range > 100 nm. Report on the specifications of the building blocks and the complete PICs has been delivered. Mask layout for the 1st run SOI was delivered and fabrication of PIC SOI and III-V wafer deliveries were carried out. Mask layout for III-V back end processing was also achieved. This 1st run layout contains demonstration PICs. 2nd generation PICs designed are compatible with EIC flip-chipping. The design specifications for the 60GBd TIA and driver has been defined. 1st generation TIA and driver test samples have been delivered for assembly. 2nd generation TIA has been designed and successfully taped-out. Design rules for the PICs have been completed allowing completion of the layouts. Packaging concept has been completed including the electrical, optical, thermal and mechanical interfaces for the PICs. Specifications in terms of optical budget and bandwidth requirements to achieve two 400 Gbps PICs for both direct-detection and coherent-detection based transmission systems were defined and summarized in a report. The testbed includes large-bandwidth digital-to-analog and analog-to-digital converters (DAC/ADC) for data generation and acquisition using state-of-the-art optical transmitters and receivers, ready for the performance evaluation of the foreseen PICs.
The large number of publications and conference papers written and presented during the course of the project are showing the level of know-how developed by PICTURE project consortium. PICTURE being strongly fabrication oriented it could potentially generate an industrial outcome and create employment either through existing consortium members or a dedicated spin-off linked to consortium members. During the course of the project, 3 Ph.D students have been involved. One of them has been recruited to continue working on silicon photonics and III-V integration as part of in-house ongoing R&D programs. In terms of technical and technological achievements, we can mention: the successful development of thin-oxide bonding technology with a high transfer efficiency, compatible with 200 mm CMOS lines, III-V dies on Si tunable DFB Lasers with III-V/Si MOSCAP DFB and successful III-V process leading to new technological developments, including Hybrid III-V on SOI SOA with record performances. Silicon MOSCAP modulators with performances at the state of the art have been obtained. Epitaxy-wise, we can mention the successful demonstration of GaInAsP-based lasers and Selective Area Growth of DFB lasers. Beyond project objectives, high-quality growth of QD lasers directly on silicon. EIC has been developed and is ready to be implemented in packaged systems (TIA+Driver). Mechanical, optical and electrical packaging design concepts have been completed.