The development of a thin bonding oxide was successfully achieved. It required the fabrication of complex silicon photonic circuits. The quality of the bonding oxide was qualified through wafer bonding of 200-mm SOI wafer and die bonding of III-V substrates. High crystalline quality of III-V material has been achieved for C-band lasers, O-band laser, modulator and photodiode stacks were successfully developed for die bonding. The fabrication of the 1st mask set on 200 mm wafers flow involved 11 levels using DUV lithography, as well as e-beam lithography. An unprecedented process flow was specifically developed for the patterning of the two sides of SOI wafers.
Both hybrid III-V/Si MOSCAP modulator-based PIC design and Si-based capacitive modulator designs have been achieved. A first-generation hybrid III-V/Si building blocks was designed including SOAs, lasers, photodiodes, and MOSCAP modulators. Demonstration PICs have been implemented on the same mask layout, taking into account the packaging constraints. As for Si-based capacitive modulators, 30Gb/s operation has been demonstrated and a new design was achieved. The Silicon MOSCAP modulators are compatible with packaging, mitigating difficulties related to hybrid III-V/Si MOSCAP hence ensuring PIC chipset delivery for PIC packaging. 2nd generation PICs are designed taking into account the flip-chipping of the EIC and the new packaging constraints including QD lasers (DFB and FP lasers) and SAG DFB lasers /modulators both grown on templates.The regrowth of MQW on InP-on-SOI was done and were compared to reference on InP. The growth and optimization of high-density InAs QDs with high photoluminescence intensity has been achieved. High-quality InAs/GaAs QDs have been demonstrated with a density of 5E10 cm-2, strong RT-PL and a narrow linewidth of <30 meV with promising initial laser results. SAG masks design has been carried out for InP on SOI templates. Fabrication process has been developed for dielectric masks. Templates were successfully patterned, enabling a wavelength emission range > 100 nm. Report on the specifications of the building blocks and the complete PICs has been delivered. Mask layout for the 1st run SOI was delivered and fabrication of PIC SOI and III-V wafer deliveries were carried out. Mask layout for III-V back end processing was also achieved. This 1st run layout contains demonstration PICs. 2nd generation PICs designed are compatible with EIC flip-chipping. The design specifications for the 60GBd TIA and driver has been defined. 1st generation TIA and driver test samples have been delivered for assembly. 2nd generation TIA has been designed and successfully taped-out. Design rules for the PICs have been completed allowing completion of the layouts. Packaging concept has been completed including the electrical, optical, thermal and mechanical interfaces for the PICs. Specifications in terms of optical budget and bandwidth requirements to achieve two 400 Gbps PICs for both direct-detection and coherent-detection based transmission systems were defined and summarized in a report. The testbed includes large-bandwidth digital-to-analog and analog-to-digital converters (DAC/ADC) for data generation and acquisition using state-of-the-art optical transmitters and receivers, ready for the performance evaluation of the foreseen PICs.
