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3D integration of a logic/memory CUBE for In-Memory-Computing

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Publications

Laser Processing for 3D junctionless transistor fabrication

Author(s): D. Bosch, P. Acosta Alba, S. Kerdiles, V. Benevent, C. Perrot, J. Lassarre, J. Richy, J. Lacord, B. Sklenard, L. Brunet, P. Batude, C. Fenouillet-Béranger, D. Lattard, J. P. Colinge, F. Balestra, F. Andrieu
Published in: IEEE S3S conference, 2019
Publisher: IEEE

High-Density 3D Monolithically Integrated Multiple 1T1R Multi-Level-Cell for Neural Networks

Author(s): E. Esmanhotto, L. Brunet, N. Castellani, D. Bonnet, T. Dalgaty, L. Grenouillet, D. R. B. Ly, C. Cagli, C. Vizioz, N. Allouti, F. Laulagnet, O. Gully, N. Bernard-Henriques, M. Bocquet, G. Molas, P. Vivet, D. Querlioz, JM. Portal, S. Mitra, F. Andrieu, C. Fenouillet-Beranger, E. Nowak, E. Vianello
Published in: 2020 IEEE International Electron Devices Meeting (IEDM), 2020, Page(s) 36.5.1-36.5.4, ISBN 978-1-7281-8888-1
Publisher: IEEE
DOI: 10.1109/iedm13553.2020.9372019

Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges

Author(s): M. Ezzadeen, A. Majumdar, M. Bocquet, B. Giraud, J.-P. Noel, F. Andrieu, D. Querlioz, J.-M. Portal
Published in: ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, Page(s) 83-86, ISBN 978-1-6654-3751-6
Publisher: IEEE
DOI: 10.1109/esscirc53450.2021.9567742

7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing

Author(s): S. Barraud, B. Previtali, C. Vizioz, J. M. Hartmann, J. Sturm, J. Lassarre, C. Perrot, Ph. Rodriguez, V. Loup, A. Magalhaes-Lucas, R. Kies, G. Romano, M. Casse, N. Bernier, A. Jannaud, A. Grenier, F. Andrieu
Published in: 2020 IEEE Symposium on VLSI Technology, 2020, Page(s) 1-2, ISBN 978-1-7281-6460-1
Publisher: IEEE
DOI: 10.1109/vlsitechnology18217.2020.9265025

3D RRAMs with Gate-All-Around Stacked Nanosheet Transistors for In-Memory-Computing

Author(s): S. Barraud, M. Ezzadeen, D. Bosch, T. Dubreuil, N. Castellani, V. Meli, J.M. Hartmann, M. Mouhdach, B. Previtali, B. Giraud, J. P. Noel, G. Molas, J.M. Portal, E. Nowak, F. Andrieu
Published in: 2020 IEEE International Electron Devices Meeting (IEDM), 2020, Page(s) 29.5.1-29.5.4, ISBN 978-1-7281-8888-1
Publisher: IEEE
DOI: 10.1109/iedm13553.2020.9371982

All-Operation-Regime Characterization and Modeling of Drain Current Variability in Junctionless and Inversion-Mode FDSOI Transistors

Author(s): D. Bosch, J. P. Colinge, G. Ghibaudo, X. Garros, S. Barraud, J. Lacord, B. Sklenard, L. Brunet, P. Batude, C. Fenouillet-Beranger, J. Cluzel, R. Kies, J. M. Hartmann, C. Vizioz, G. Audoit, F. Balestra, F. Andrieu
Published in: 2020 IEEE Symposium on VLSI Technology, 2020, Page(s) 1-2, ISBN 978-1-7281-6460-1
Publisher: IEEE
DOI: 10.1109/vlsitechnology18217.2020.9265036

Comparative experimental study of junctionless and inversion-mode nanowire transistors for analog applications

Author(s): D. Bosch, J.P. Colinge, J. Lugo, A. Tataridou, C. Theodorou, X. Garros, S. Barraud, J. Lacord, B. Sklenard, M. Casse, L. Brunet, P. Batude, C. Fenouillet-Beranger, D. Lattard, J. Cluzel, F. Allain, R. Nait Youcef, J.M. Hartmann, C. Vizioz, G. Audoit, F. Balestra, F. Andrieu
Published in: 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2020, Page(s) 126-127, ISBN 978-1-7281-4232-6
Publisher: IEEE
DOI: 10.1109/vlsi-tsa48913.2020.9203690

First Demonstration of Low Temperature (≤500°C) CMOS Devices Featuring Functional RO and SRAM Bitcells toward 3D VLSI Integration

Author(s): C. Fenouillet-Beranger, L. Brunet, P. Batude, L. Brevard, X. Garros, T. Mota Frutuoso, M. Casse, J. Lugo, J. Lacord, D. Bosch, N. Bernard, A. Magalhaes-Lucas, M. Ribotta, B. Sklenard, F. Milesi, R. Kies, G. Romano, P. Acosta-Alba, S. Kerdiles, A. Tavernier, C. Vizioz, P. Besson, R. Gassilloud, J. Kanyandekwe, D. Cooper, V. Lapras, W. H. Kim, Y. Sasaki, S. Oh, P. Kang, S. W. Lee, H. Na, J. Arcamone
Published in: 2020 IEEE Symposium on VLSI Technology, 2020, Page(s) 1-2, ISBN 978-1-7281-6460-1
Publisher: IEEE
DOI: 10.1109/vlsitechnology18217.2020.9265092

A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration

Author(s): C. Fenouillet-Beranger, L. Brunet, P. Batude, L. Brevard, X. Garros, M. Casse, J. Lacord, B. Sklenard, P. Acosta-Alba, S. Kerdiles, A. Tavernier, C. Vizioz, P. Besson, R. Gassilloud, J.-M. Pedini, J. Kanyandekwe, F. Mazen, A. Magalhaes-Lucas, C. Cavalcante, D. Bosch, M. Ribotta, V. Lapras, M. Vinet, F. Andrieu, J. Arcamone
Published in: IEEE Transactions on Electron Devices, 68/7, 2021, Page(s) 3142-3148, ISSN 0018-9383
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2021.3084916

Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications

Author(s): M. Ezzadeen, D. Bosch, B. Giraud, S. Barraud, J. -P. Noel, D. Lattard, J. Lacord, J. M. Portal, F. Andrieu
Published in: IEEE Transactions on Electron Devices, 67/11, 2020, Page(s) 4626-4630, ISSN 0018-9383
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2020.3020779