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3D integration of a logic/memory CUBE for In-Memory-Computing

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Publications

Laser Processing for 3D junctionless transistor fabrication

Author(s): D. Bosch, P. Acosta Alba, S. Kerdiles, V. Benevent, C. Perrot, J. Lassarre, J. Richy, J. Lacord, B. Sklenard, L. Brunet, P. Batude, C. Fenouillet-Béranger, D. Lattard, J. P. Colinge, F. Balestra, F. Andrieu
Published in: IEEE S3S conference, 2019

All-operation-regime characterization and modeling of drain current variability in junctionless and inversion-mode FDSOI transistors

Author(s): D. Bosch, J.P. Colinge, G. Ghibaudo, X. Garros, S. Barraud, J. Lacord, B. Sklenard, L. Brunet, P. Batude, C. Fenouillet-Béranger, J. Cluzel, R. Kies, J.M. Hartmann, C. Vizioz, G. Audoit, F. Balestra, F. Andrieu
Published in: IEEE Symposium of VLSI Technology, 2020

Comparative experimental study of junctionless and inversion-mode nanowire transistors for analog applications

Author(s): D. Bosch, J.P. Colinge, J. Lugo, A. Tataridou, C. Theodorou, X. Garros, S. Barraud, J. Lacord, B. Sklenard, M. Casse, L. Brunet, P. Batude, C. Fenouillet-Beranger, D. Lattard, J. Cluzel, F. Allain, R. Nait Youcef, J.M. Hartmann, C. Vizioz, G. Audoit, F. Balestra, F. Andrieu
Published in: 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2020, Page(s) 126-127
DOI: 10.1109/vlsi-tsa48913.2020.9203690

Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications

Author(s): M. Ezzadeen, D. Bosch, B. Giraud, S. Barraud, J. -P. Noel, D. Lattard, J. Lacord, J. M. Portal, F. Andrieu
Published in: IEEE Transactions on Electron Devices, Issue 67/11, 2020, Page(s) 4626-4630, ISSN 0018-9383
DOI: 10.1109/ted.2020.3020779