Periodic Reporting for period 1 - TERIPHIC (Fabrication and assembly automation of TERabit optical transceivers based on InP EML arrays and a Polymer Host platform for optical InterConnects up to 2 km and beyond)
Reporting period: 2019-01-01 to 2020-06-30
Figure 1 is an artistic layout of the TERIPHIC 800Gb/s pluggable transceiver module (left) and the 1.6 Tb/s mid-board transceiver module for the next generation intra-DC interfaces (right).
To do that, TERIPHIC will simplify the design of the transceivers by reducing the number of interfaces to be integrated and will develop the necessary hardware for the automation of the assembly process. To achieve the first, TERIPHIC will combine arrays of multi-functional components such as InP EMLs and high speed InP PDs with a low-cost polymer motherboard that will also perform MUX/DEMUX functionalities. To achieve the latter, TERIPHIC will modify commercial photonic assembly machines, by building custom gripper arms. The result will be Terabit transceiver modules which cost less than 1 €/Gbps.
WP2: System design and definition of integration and packaging engine
The system requirements for intra-DC interconnects and application scenarios of TERIPHIC transceivers have been defined and have been translated into component specifications. The high level designs of the first pluggable transceiver modules have been produced and the module assembly and packaging processes have been defined considering all the challenges. System models of these transceivers were prepared, and simulations were carried out to assess the system performance. Several DSP methods for both the Tx and Rx parts have been assessed. Preliminary experiments using test equipment were realized.
WP3: Development of components and integration engine for Terabit optical subassemblies (Fig. 3)
The design and fabrication of the first generation of photonic components has been completed and the major targets in terms of performance have been met. The first generation components comprised the quad InP EML array, the quad InP PD array, 4-ch and 8-ch AWG on PolyBoard, that will also act as the motherboards and the 4-ch and 8-ch polymer FlexLines for high speed electrical interconnection. The EMLs achieved approx.. 40 GHz 3-d bandwidth, the PDs approx. 50 GHz and the polymer FlexLines > 100 GHz, making them appropriate for 56 GBaud PAM-4 operation. The 4-ch TOSA/ROSA have been assembled and will be used for the assembly and packaging of the first 400Gb/s pluggable transceiver module. The automated assembly process has been defined, the custom gripper arm that can handle the arrays of active components has been fabricated, and the software algorithm for the automated assembly process has been developed.
WP4: Development of InP-DHBT linear driver arrays and selection of BiCMOS electronics
TERIPHIC will rely on the use of commercial BiCMOS electronic driving and TIA chips for the pluggable transceiver modules due to their low cost and low power consumption. The BiCMOS chips for the Tx and Rx were selected from a pool of candidate chips from different vendors. A 400G DSP chip with integrated 4-ch driver array will drive the EML array, while a 4-ch TIA will amplify the signals from the PD array. The InP-DHBT linear driver (Fig. 3) array building blocks have been designed, fabricated, characterized and achieved the high bandwidth and power consumption targets. These building block will be used in the quad linear driver array which is currently under design.
WP5: Packaging of TERIPHIC modules
The packaging processes for the TERIPHIC pluggable and mid-board modules have been defined, considering the all the technical issues that were brought along with the innovations. The process for the interconnection of the EMLs/PDs with the electronic driving chips using FlexLines was defined. The TERIPHIC transceivers will be packaged in MSA compatible packages targeting high TRL. Mechanical and thermal simulations were carried out considering the mechanical dimensions and thermal dissipation of the active components. The transceiver mainboards that will host all the electronic and photonic components are being designed.
WP6: System integration, testing and performance evaluation
The benchmarking procedures for the characterization of the TERIPHIC devices were defined at the component level, at the system link level, and at the network level. For each level of testing the testing methodology was defined along with the experimental testbeds. The TERIPHIC pluggable and mid-board transceiver modules will be tested at lab settings with test equipment, in intra-DC settings for shorter reach links up to 2km and in inter-DC network settings for longer links up to 10 km. An evaluation board comprising a 4-ch TOSA/ROSA and a 400G DSP chip was designed and fabricated as a precursor to module 1, to verify the potential of the TERIPHIC concept.
WP7: Dissemination and exploitation activities, roadmaps and manufacturability studies
Exploitation plans for each partner were generated and dissemination actions were performed aiming to spread the word for TERIPHIC. Main channels were conference presentations, a news story that was published to major online technology magazines related to laser technology and photonics such as Laser Focus World, Optics, Electronics World, Science Business etc., the project website which also features a short video presenting TERIPHIC to the general public. One conference talk at high profile conference presented TERIPHIC concept. Market surveys and technology roadmaps were analyzed to ensure the project targets remain relevant and impactful after the project end. IPR in relevant topics were tracked and evaluated.