The main technical achievements of TERIPHIC can be summarized as follows:
WP2: System design and definition of integration and packaging engine
The system requirements for intra-DC interconnects and application scenarios of TERIPHIC transceivers have been defined and have been translated into component specifications. The transceiver module designs have been produced and the packaging processes have been defined. Updated simulations studies were carried out to assess the system performance. Preliminary experiments using test equipment were realized. The simulation results have been compared with results from the experimental characterization of the optical subassemblies and devices and are in good agreement.
WP3: Development of components and integration engine for Terabit optical subassemblies (Fig. 3)
The second generation of photonic components including 8-fold EML and PD arrays, 8-ch AWG and 16-ch AWG polymer motherboards were fabricated. The 8-fold EMLs achieved approx. 40 GHz 3-d bandwidth, the PDs approx. 50 GHz making them appropriate for 56 GBaud PAM-4 operation. The 8-fold EMLs were fabricated at two batches covering the 1273 – 1291 nm and 1293 – 1309 nm wavelength range that is compatible with FR8 GbE wavelength grid. The custom gripper tool for automatically assembling up to 8-fold EML/PD arrays to PolyBoards was developed and installed at HHI’s assembly machine. 400Gb/s TOSA/ROSA and 800Gb/s TOSA/ROSAs have been assembled for the 400Gb/s transceiver and 800Gb/s transceiver using a semi-automated assembly process while the fully automated process was in development. The fully automated process demonstrated the capability to automatically handle the 8-fold EML and PD arrays, align them on the PolyBoard motherboards and fix them in place. A unified process was developed to handle the EML and PD arrays in the same way. Moreover, an automated process for the fiber pigtailing has been developed, facilitating the assembly and providing a solution for the two main processes in fabrication of the TOSAs/ROSAs.
WP4: Development of InP-DHBT linear driver arrays and selection of BiCMOS electronics
400G and 800G DSP chips were selected to be integrated on the TERIPHIC transceivers. The second-generation quad-channel InP-DHBT linear driver devices were measured up to 64 GBd and show very good performances, with a 1.8-Vppse linear PAM-4 output swing at 0.75-W/channel power consumption, while the quad-driver die dimensions were decreased down to 2.4x1.5 mm². Although the total area is kept constant, the lateral dimension, that is critical for the driver integration into the TERIPHIC modules, was decreased by around 33%, imposing stringent design rules and a complete redraw of the driver core implantation. The InP-DHBT quad driver performance has resulted in top scoping publications.
WP5: Packaging of TERIPHIC modules
The design work of the transceiver PCBs, including layouting and mechanical designs were completed and the PCBs were fabricated in state of the art PCB materials having up to 10 layers. The PCBs have been designed having in mind a proof-of-concept approach for TERIPHIC technology, but considering also form-factor compatibility to the most common pluggable (e.g. OSFP) and mid-board (e.g. COBO-16) form-factors.
WP6: System integration, testing and performance evaluation
The experimental testbeds at lab settings and at the system vendor and network operator settings were setup for the characterization of TERIPHIC's components and TOSAs/ROSAs.
The tests of TERIPHIC TOSAs/ROSAs for the 400Gb/s and 800Gb/s transceivers have demonstrated successful operation at 53Gbaud PAM-4. Optical transmission tests have been carried out for typical distances in intra-DC networks: 2km (with good resutls) and 10km (with satisfactory results). A full link was also successfully established between the Tx the Rx channel of the same TOSA/ROSA. The network operator successfully integrated NVIDIA’s switches with their SDN controller and have realized trials using commercial pluggable transceiver modules on field installed fiber, setting up benchmark tests for the TERIPHIC transceivers.
WP7: Dissemination and exploitation activities, roadmaps and manufacturability studies
Each partner developped its individual exploitation and business plan. Six publications acknowledging TERIPHIC have been submitted to prestigious journals and conferences. Dissemination activities have maximized the vilsibility of the project. Technoeconomic analysis have been carried out. Market surveys and technology roadmaps were analyzed to ensure the project targets remain relevant and impactful after the project end. IPR in relevant topics are tracked and evaluated.
