Periodic Reporting for period 2 - TERIPHIC (Fabrication and assembly automation of TERabit optical transceivers based on InP EML arrays and a Polymer Host platform for optical InterConnects up to 2 km and beyond)
Período documentado: 2020-07-01 hasta 2021-12-31
Figure 1 (left) presents the optical engine that sits at the heart of the transceiver, and is based on the hybrid integration (edge coupling) of the EML/PD arrays with a polymer motherboard. (right) the edge-coupling process of an EML array to PolyBoard using the custom gripper tool
To do that, TERIPHIC will simplify the design of the transceivers by reducing the number of interfaces to be integrated and will develop the necessary hardware for the automation of the assembly process. To achieve the first, TERIPHIC will combine arrays of multi-functional components such as InP EMLs and high speed InP PDs with a low-cost polymer motherboard that will also perform MUX/DEMUX functionalities. To achieve the latter, TERIPHIC will modify commercial photonic assembly machines, by building custom gripper arms. The result will be Terabit transceiver modules which cost less than 1 €/Gbps.
WP2: System design and definition of integration and packaging engine
The system requirements for intra-DC interconnects and application scenarios of TERIPHIC transceivers have been defined and have been translated into component specifications. The transceiver module designs have been produced and the packaging processes have been defined. Updated simulations studies were carried out to assess the system performance. Preliminary experiments using test equipment were realized.
WP3: Development of components and integration engine for Terabit optical subassemblies (Fig. 3)
The second generation of photonic components including 8-fold EML and PD arrays, 8-ch AWG polymer motherboards have been fabricated. The EMLs achieved approx. 40 GHz 3-d bandwidth, the PDs approx. 50 GHz making them appropriate for 56 GBaud PAM-4 operation. The custom gripper tool for automatically assembling up to 8-fold EML/PD arrays to PolyBoards has been developed and is installed at HHI’s assembly machine. Four 400Gb/s TOSA/ROSA have been assembled and 800Gb/s TOSA/ROSAs are in the making. 4-ch and 8-ch FlexLines with pitch adaptation have been developed and a proof-of-concept flip-chip fixation method developed.
WP4: Development of InP-DHBT linear driver arrays and selection of BiCMOS electronics
400G DSP chips have been selected to be integrated on the 400G transceivers. Moreover, state of the art 5nm 800G DSP platform, that has only recently hit the market, has been secured and will power the 800G and 1.6T TERIPHIC transceivers.
Two generations of quad InP-DHBT linear driver (Fig. 3) arrays have been developed, capable of 64GBaud PAM-4 operation, with <0.8W/channel power consumption, achieving 30% reduction in the. footprint of the 2nd gen. drivers compared to the 1st gen.
WP5: Packaging of TERIPHIC modules
The design work of the transceiver PCBs, including layouting and mechanical designs has progressed and is available for all modules. Packaging processes for the TERIPHIC pluggable and mid-board modules have been defined, considering the all the technical issues that were brought along with the innovations. The performance of the assembly process of FlexLines is being evaluated. TERIPHIC’s most complex module, the 1.6T will accommodate two 800G DSP chips and four quad InP-DHBT linear driver arrays.
WP6: System integration, testing and performance evaluation
The experimental testbeds at lab settings and at the system vendor and network operator settings are setup and available. The TERIPHIC pluggable and mid-board transceiver modules will be tested at lab settings with test equipment, and then in intra-DC settings for shorter reach links up to 2km and in inter-DC network settings for longer links up to 10 km. An evaluation board comprising a 4-ch TOSA/ROSA and a 400G DSP chip is being assembled as a precursor to module 1, to verify the potential of the TERIPHIC concept. Modulation tests with EML arrays on chip subcarriers have been realized showing good large signal performance up to 53 Gbaud.
WP7: Dissemination and exploitation activities, roadmaps and manufacturability studies
Individual exploitation and business plans for each partner were generated and are continuously updated. Six publications acknowledging TERIPHIC have been submitted to prestigious journals and conferences. Dissemination activities through the website, social media, the promotion video and workshop presentations, are progressing well and visibility is increasing. Technoeconomic analysis have been carried out. Market surveys and technology roadmaps are analyzed to ensure the project targets remain relevant and impactful after the project end. IPR in relevant topics are tracked and evaluated.