Periodic Reporting for period 2 - PIN3S (Pilot Integration of 3nm Semiconducter technology)
Période du rapport: 2020-10-01 au 2021-11-30
The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers development and integration of 3nm process modules, advanced lithography equipment, patterning technology, metrology and supplementing the Extreme UV (EUV) mask infrastructure with mask repair equipment, process and repair strategies.
In lithography the main objectives are the introduction of a new tool for the Deep UV (DUV) immersion technology and the integration and validation of the first hyper Numerical Aperture tool for the EUV technology. In DUV there will be the introduction of a distortion manipulator to achieve the tighter imaging overlay requirements.
The aim in metrology is to develop 3D dimensional and compositional measurement solutions capable to address the new 3nm node device architectures.
The key objective in Process Integration is the integration of a device meeting the 3nm node Performance, Power, Area and Cost (PPAC) requirements. This covers, device architecture selection, integration of innovative process solutions in Front End Of Line (FEOL), Middle Of Line (MOL) and Back End of Line (BEOL) modules and finally demonstration of a fully integrated electrical device. Given that EUV multi-patterning is key to resolve the targeted pitches, a dedicated task addresses the EUV resist readiness for high volume manufacturing (HVM).
In lithography the main objectives are the introduction of a new tool for the Deep UV (DUV) immersion technology and the integration and validation of the first hyper Numerical Aperture tool for the EUV technology. In DUV there will be the introduction of a distortion manipulator to achieve the tighter imaging overlay requirements.
The aim in metrology is to develop 3D dimensional and compositional measurement solutions capable to address the new 3nm node device architectures.
The key objective in Process Integration is the integration of a device meeting the 3nm node Performance, Power, Area and Cost (PPAC) requirements. This covers, device architecture selection, integration of innovative process solutions in Front End Of Line (FEOL), Middle Of Line (MOL) and Back End of Line (BEOL) modules and finally demonstration of a fully integrated electrical device. Given that EUV multi-patterning is key to resolve the targeted pitches, a dedicated task addresses the EUV resist readiness for high volume manufacturing (HVM).
To date, the first system qualification of the 3nm DUV immersion scanner took place. A second iteration of the distortion manipulator has been integrated in a DUV immersion scanner, showing record-level imaging results. In regard to the hyper-NA EUV system, the first deliveries of sub-systems have been realized and shipped such as the power cabinets and large frame supporting the EUV Source. Other component manufacturing such as the illumination system has made significant progress
A 3nm node mask repair prototype system was specified, designed, built and integrated. As a key module, a novel repair-specific aberration-corrected E-beam column was developed and provisioned. Using the prototype system, the feasibility of high-resolution mask repair etches was successfully demonstrated in line with 3nm node requirements. Furthermore, a first version of an Artificial Intelligence based mask defect- and repair assessment tool was developed, and an underlying mask defect detection network was developed, trained and optimized. Finally, a new SEM-FIB-EDX system was provisioned and successfully used for the analysis of mask repair samples.
In Metrology, THERMO’s “Alpha” Energy Dispersive X-ray prototypes were confirmed to meet specifications and to reproduce low energy resolution (Figure 4). Applied Materials developed a fast Scan Electron Microscopy platform and application, and completed new HW and control SW realizing a reduction of 3.2 to 6x in time to recipe (Figure 5).
In addition, a novel electro-magnetic interference and acoustic noise suppression enclosure to improve noise shielding was qualified.
NOVA explored an additional algorithmic method which accelerate spectra library creation for high aspect ratio feature characterization.
KLA Israel demonstrated new and accurate on-resist-target e-Beam overlay metrology.
In Process Integration, the Gate All Around Nanosheet (GAA NS) was selected for the 3nm node. FEOL and MOL module development yielded progress related to low-k inner spacers, in-situ doped S/D integration, new ‘zero thickness’ electrical Work Function Metals (eWFM) shifters, heavy-metals silicides for low contact resistivity and design/implementation options selection for the integration of Buried Power Rails (BPR) and Via to Buried Power Rails (VBPR) scaling boosters in 3nm node CMOS technology.
BEOL module integration yielded progress related to: semi-damascene integration including first 18nm metal pitch results, electrical validation of low resistive Super Via scaling booster and first results, morphological and electrical, related to Air Gap isolation integration. Related to EUV for HVM, achievements include software development for more efficient capturing of stochastic defects, stochastic defects reduction through point of use resist filtration and improved post development rinse. The development of an electrical vehicle for the quantitative study of process windows for stochastic defectivity. And finally, resist screening for 28nm pitch for SE EUV.
A 3nm node mask repair prototype system was specified, designed, built and integrated. As a key module, a novel repair-specific aberration-corrected E-beam column was developed and provisioned. Using the prototype system, the feasibility of high-resolution mask repair etches was successfully demonstrated in line with 3nm node requirements. Furthermore, a first version of an Artificial Intelligence based mask defect- and repair assessment tool was developed, and an underlying mask defect detection network was developed, trained and optimized. Finally, a new SEM-FIB-EDX system was provisioned and successfully used for the analysis of mask repair samples.
In Metrology, THERMO’s “Alpha” Energy Dispersive X-ray prototypes were confirmed to meet specifications and to reproduce low energy resolution (Figure 4). Applied Materials developed a fast Scan Electron Microscopy platform and application, and completed new HW and control SW realizing a reduction of 3.2 to 6x in time to recipe (Figure 5).
In addition, a novel electro-magnetic interference and acoustic noise suppression enclosure to improve noise shielding was qualified.
NOVA explored an additional algorithmic method which accelerate spectra library creation for high aspect ratio feature characterization.
KLA Israel demonstrated new and accurate on-resist-target e-Beam overlay metrology.
In Process Integration, the Gate All Around Nanosheet (GAA NS) was selected for the 3nm node. FEOL and MOL module development yielded progress related to low-k inner spacers, in-situ doped S/D integration, new ‘zero thickness’ electrical Work Function Metals (eWFM) shifters, heavy-metals silicides for low contact resistivity and design/implementation options selection for the integration of Buried Power Rails (BPR) and Via to Buried Power Rails (VBPR) scaling boosters in 3nm node CMOS technology.
BEOL module integration yielded progress related to: semi-damascene integration including first 18nm metal pitch results, electrical validation of low resistive Super Via scaling booster and first results, morphological and electrical, related to Air Gap isolation integration. Related to EUV for HVM, achievements include software development for more efficient capturing of stochastic defects, stochastic defects reduction through point of use resist filtration and improved post development rinse. The development of an electrical vehicle for the quantitative study of process windows for stochastic defectivity. And finally, resist screening for 28nm pitch for SE EUV.
Virtually all technology developed within the PIn3S project is beyond state of the art. The new DUV immersion tool has multiple new modules incorporated in it such as advanced imaging correction models and material coatings. The distortion manipulator technology is completely new for both DUV and EUV. It allows for local wave-front correction, greatly reducing overlay errors enabling to bring the On Product Overlay from 2.5nm to 1.5nm. The hyper-NA EUV scanner required major innovations on many fronts such as manufacturing techniques, particle contamination and dynamic behavior due to 4x acceleration of the reticle stage with respect to the previous generation EUV scanners.
PIn3S shall push mask repair towards the 3nm node performance which is well beyond the present state of the art. To achieve this, a mask repair tool prototype system including a novel repair-specific-aberration-corrected E-beam column was developed and built. First mask repair etches were generated using the prototype system. The first etches demonstrated a mask repair resolution of better than 7nm which is already well in line with 3nm node mask repair requirements. Furthermore, Artificial Intelligence was used for the first time in a mask defect- and repair assessment tool showing a 100% defect detection rate for several mask pattern types. Finally, the mask sample analysis technology has been extended by combining SEM-FIB-EDX mask sample measurements with AFM and TEM data.
In metrology progress beyond state of the art includes new generation of metrology and inspection tools which will be ready for the 3nm technology node challenges such as to maximize the capture of stochastic defects, high aspect ratio features in the front and back end of line and overlay accuracy which stem from optical 3D effects. The solution will serve the most advanced fabs worldwide for high-volume manufacturing of next generation logic and memory devices.
In process integration beyond state of the art include: low-k dielectrics for gate spacer and inner spacer, ‘zero thickness’ Work Function Metal shifters for Replacement Metal Gate module, highly in-situ doped S/D and heavy metals for low resistivity contacts. In BEOL, Self-Aligned Via for multi-level semi-damascene, low resistive Ru and Air Gap for RC delay reduction, and low resistive Super Via scaling booster for interconnect congestion reduction.
PIn3S shall push mask repair towards the 3nm node performance which is well beyond the present state of the art. To achieve this, a mask repair tool prototype system including a novel repair-specific-aberration-corrected E-beam column was developed and built. First mask repair etches were generated using the prototype system. The first etches demonstrated a mask repair resolution of better than 7nm which is already well in line with 3nm node mask repair requirements. Furthermore, Artificial Intelligence was used for the first time in a mask defect- and repair assessment tool showing a 100% defect detection rate for several mask pattern types. Finally, the mask sample analysis technology has been extended by combining SEM-FIB-EDX mask sample measurements with AFM and TEM data.
In metrology progress beyond state of the art includes new generation of metrology and inspection tools which will be ready for the 3nm technology node challenges such as to maximize the capture of stochastic defects, high aspect ratio features in the front and back end of line and overlay accuracy which stem from optical 3D effects. The solution will serve the most advanced fabs worldwide for high-volume manufacturing of next generation logic and memory devices.
In process integration beyond state of the art include: low-k dielectrics for gate spacer and inner spacer, ‘zero thickness’ Work Function Metal shifters for Replacement Metal Gate module, highly in-situ doped S/D and heavy metals for low resistivity contacts. In BEOL, Self-Aligned Via for multi-level semi-damascene, low resistive Ru and Air Gap for RC delay reduction, and low resistive Super Via scaling booster for interconnect congestion reduction.