To date, the first system qualification of the 3nm DUV immersion scanner took place with an integrated distortion manipulator, see Figure 2. The system qualification showed that the main Key performance Indicators of the lithography system were in line with the 3nm node system requirements. In regard to the hyper-NA EUV system, all mechatronic parts of the system have been integrated and qualified, both individually and in conjunction with each other, see Figure 1. One of the two optical modules (the illuminator) has been delivered and integrated as well.
A 3nm node mask repair prototype system was specified, designed, built and integrated. Using the prototype system, the feasibility of high-resolution mask repair etches was successfully demonstrated in line with 3nm node requirements. The repair results were validated for an EUV test-mask with programmed defects by electro-optical methods. Furthermore, a first version of an Artificial Intelligence based mask defect- and repair assessment tool was developed, and an underlying mask defect detection network was developed, trained and optimized. Finally, a new SEM-FIB-EDX system was provisioned and successfully used for the analysis of mask repair samples, see Figure 3.
In Metrology, Applied Materials Israel developed a fast Scan Electron Microscopy platform and application (together with Applied Material Belgium), and completed new HW and control SW realizing a reduction of up to 6x in time to recipe and local CDU and hotspot with factor of 2 – 3 of measurements per hour on imec samples (Figure 4).
THERMO has completed demonstrating using the new Ultra-X EDX module high resolution, high speed and low energy X-ray material detection, with high throughput on imec’s Forksheet samples; NOVA completed the development of a new Vertical Traveling Wave (VTW) algorithm and obtained significant acceleration of the optical critical dimension (OCD) high aspect ratio (HAR); and KTI achieved the goal of developing e-beam overlay target selection and optimization methodology, best suited for 3nm technology node.
In Process Integration, the Gate All Around Nanosheet (GAA NS) architecture was selected for the 3nm node. FEOL and MOL module development yielded progress related to inner spacers, in-situ doped S/D and heavy-metals silicides for low resistivity contacts, and electrical Work Function Metals (eWFM) integration. The progress cumulated in the demonstration of electrical functional GAA NS devices, see Figure 8. Also module development for Buried Power Rails (BPR) was completed, see Figure 5.
BEOL module integration yielded solutions, including electrical validation, for respectively dual damascene integration at 21nm metal pitch, semi-damascene integration at 18nm metal pitch. Scaling booster integration comprised module development for Super Via, and Air Gap isolation. Related to EUV for HVM, work included extensive photo resist studies for 0.33NA EUV single exposure for 28nm pitch lines/spaces and 34nm Center-to-Center contacts/pillars use cases, see Figure 7, the development of an electrical vehicle for the quantitative study of process windows for stochastic defects, see Figure 8.
Hardware developments comprised, advanced purge system for sorters (Recif) and mock-up for contamination (airborne, particles) monitoring in reticle pod (Pfeiffer).
