Periodic Reporting for period 3 - PIN3S (Pilot Integration of 3nm Semiconducter technology)
Período documentado: 2021-12-01 hasta 2023-04-30
The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers development and integration of 3nm process modules, advanced lithography equipment, patterning technology, metrology and supplementing the Extreme UV (EUV) mask infrastructure with mask repair equipment, process and repair strategies.
In lithography the main objectives are the introduction of a new tool for the Deep UV (DUV) immersion technology and the integration and validation of the first hyper Numerical Aperture tool for the EUV technology. In DUV there will be the introduction of a distortion manipulator to achieve the tighter imaging overlay requirements.
The aim in metrology is to develop 3D dimensional and compositional measurement solutions capable to address the new 3nm node device architectures.
For mask repair equipment, the objective is to realize mask repair equipment with a new aberration corrected ultra-low energy E-beam column capable to meet the 3nm node technology requirements.
The key objective in Process Integration is the integration of a device meeting the 3nm node Performance, Power, Area and Cost (PPAC) requirements. This covers, device architecture selection, integration of innovative process solutions in Front End of Line (FEOL), Middle of Line (MOL) and Back End of Line (BEOL) modules and finally demonstration of a fully integrated electrical device. Given that EUV patterning is key to resolve the targeted pitches, a dedicated task addresses the EUV resist readiness for high volume manufacturing (HVM).
In lithography the main objectives are the introduction of a new tool for the Deep UV (DUV) immersion technology and the integration and validation of the first hyper Numerical Aperture tool for the EUV technology. In DUV there will be the introduction of a distortion manipulator to achieve the tighter imaging overlay requirements.
The aim in metrology is to develop 3D dimensional and compositional measurement solutions capable to address the new 3nm node device architectures.
For mask repair equipment, the objective is to realize mask repair equipment with a new aberration corrected ultra-low energy E-beam column capable to meet the 3nm node technology requirements.
The key objective in Process Integration is the integration of a device meeting the 3nm node Performance, Power, Area and Cost (PPAC) requirements. This covers, device architecture selection, integration of innovative process solutions in Front End of Line (FEOL), Middle of Line (MOL) and Back End of Line (BEOL) modules and finally demonstration of a fully integrated electrical device. Given that EUV patterning is key to resolve the targeted pitches, a dedicated task addresses the EUV resist readiness for high volume manufacturing (HVM).
To date, the first system qualification of the 3nm DUV immersion scanner took place with an integrated distortion manipulator, see Figure 2. The system qualification showed that the main Key performance Indicators of the lithography system were in line with the 3nm node system requirements. In regard to the hyper-NA EUV system, all mechatronic parts of the system have been integrated and qualified, both individually and in conjunction with each other, see Figure 1. One of the two optical modules (the illuminator) has been delivered and integrated as well.
A 3nm node mask repair prototype system was specified, designed, built and integrated. Using the prototype system, the feasibility of high-resolution mask repair etches was successfully demonstrated in line with 3nm node requirements. The repair results were validated for an EUV test-mask with programmed defects by electro-optical methods. Furthermore, a first version of an Artificial Intelligence based mask defect- and repair assessment tool was developed, and an underlying mask defect detection network was developed, trained and optimized. Finally, a new SEM-FIB-EDX system was provisioned and successfully used for the analysis of mask repair samples, see Figure 3.
In Metrology, Applied Materials Israel developed a fast Scan Electron Microscopy platform and application (together with Applied Material Belgium), and completed new HW and control SW realizing a reduction of up to 6x in time to recipe and local CDU and hotspot with factor of 2 – 3 of measurements per hour on imec samples (Figure 4).
THERMO has completed demonstrating using the new Ultra-X EDX module high resolution, high speed and low energy X-ray material detection, with high throughput on imec’s Forksheet samples; NOVA completed the development of a new Vertical Traveling Wave (VTW) algorithm and obtained significant acceleration of the optical critical dimension (OCD) high aspect ratio (HAR); and KTI achieved the goal of developing e-beam overlay target selection and optimization methodology, best suited for 3nm technology node.
In Process Integration, the Gate All Around Nanosheet (GAA NS) architecture was selected for the 3nm node. FEOL and MOL module development yielded progress related to inner spacers, in-situ doped S/D and heavy-metals silicides for low resistivity contacts, and electrical Work Function Metals (eWFM) integration. The progress cumulated in the demonstration of electrical functional GAA NS devices, see Figure 8. Also module development for Buried Power Rails (BPR) was completed, see Figure 5.
BEOL module integration yielded solutions, including electrical validation, for respectively dual damascene integration at 21nm metal pitch, semi-damascene integration at 18nm metal pitch. Scaling booster integration comprised module development for Super Via, and Air Gap isolation. Related to EUV for HVM, work included extensive photo resist studies for 0.33NA EUV single exposure for 28nm pitch lines/spaces and 34nm Center-to-Center contacts/pillars use cases, see Figure 7, the development of an electrical vehicle for the quantitative study of process windows for stochastic defects, see Figure 8.
Hardware developments comprised, advanced purge system for sorters (Recif) and mock-up for contamination (airborne, particles) monitoring in reticle pod (Pfeiffer).
A 3nm node mask repair prototype system was specified, designed, built and integrated. Using the prototype system, the feasibility of high-resolution mask repair etches was successfully demonstrated in line with 3nm node requirements. The repair results were validated for an EUV test-mask with programmed defects by electro-optical methods. Furthermore, a first version of an Artificial Intelligence based mask defect- and repair assessment tool was developed, and an underlying mask defect detection network was developed, trained and optimized. Finally, a new SEM-FIB-EDX system was provisioned and successfully used for the analysis of mask repair samples, see Figure 3.
In Metrology, Applied Materials Israel developed a fast Scan Electron Microscopy platform and application (together with Applied Material Belgium), and completed new HW and control SW realizing a reduction of up to 6x in time to recipe and local CDU and hotspot with factor of 2 – 3 of measurements per hour on imec samples (Figure 4).
THERMO has completed demonstrating using the new Ultra-X EDX module high resolution, high speed and low energy X-ray material detection, with high throughput on imec’s Forksheet samples; NOVA completed the development of a new Vertical Traveling Wave (VTW) algorithm and obtained significant acceleration of the optical critical dimension (OCD) high aspect ratio (HAR); and KTI achieved the goal of developing e-beam overlay target selection and optimization methodology, best suited for 3nm technology node.
In Process Integration, the Gate All Around Nanosheet (GAA NS) architecture was selected for the 3nm node. FEOL and MOL module development yielded progress related to inner spacers, in-situ doped S/D and heavy-metals silicides for low resistivity contacts, and electrical Work Function Metals (eWFM) integration. The progress cumulated in the demonstration of electrical functional GAA NS devices, see Figure 8. Also module development for Buried Power Rails (BPR) was completed, see Figure 5.
BEOL module integration yielded solutions, including electrical validation, for respectively dual damascene integration at 21nm metal pitch, semi-damascene integration at 18nm metal pitch. Scaling booster integration comprised module development for Super Via, and Air Gap isolation. Related to EUV for HVM, work included extensive photo resist studies for 0.33NA EUV single exposure for 28nm pitch lines/spaces and 34nm Center-to-Center contacts/pillars use cases, see Figure 7, the development of an electrical vehicle for the quantitative study of process windows for stochastic defects, see Figure 8.
Hardware developments comprised, advanced purge system for sorters (Recif) and mock-up for contamination (airborne, particles) monitoring in reticle pod (Pfeiffer).
Virtually all technology developed within the PIn3S project is beyond state of the art. The new DUV immersion tool has multiple new modules incorporated in it such as advanced imaging correction models and material coatings. The distortion manipulator technology is completely new for both DUV and EUV. It allows for local wave-front correction, greatly reducing overlay errors enabling to bring the On Product Overlay from 2.5nm to 1.5nm. The hyper-NA EUV scanner required major innovations on many fronts such as manufacturing techniques, particle contamination and dynamic behavior due to 4x acceleration of the reticle stage with respect to the previous generation EUV scanners.
PIn3S shall push mask repair towards the 3nm node performance which is well beyond the present state of the art. To achieve this, a mask repair tool prototype system including a novel repair-specific-aberration-corrected E-beam column was developed and built. Repair etches demonstrated a mask repair resolution in line with the 3nm node mask repair requirements. Additionally, repair success was validated for a Process-Of-Record POR EUV test mask with programmed defects using SEM and aerial image measurements (AIMS). Furthermore, Artificial Intelligence was used for the first time in a mask defect- and repair assessment tool showing a 100% defect detection rate for several mask pattern types. Finally, the mask sample analysis technology has been extended by combining SEM-FIB-EDX mask sample measurements with AFM and TEM data.
In metrology progress beyond state of the art includes new generation of metrology and inspection tools which will be ready for the 3nm technology node challenges such as to maximize the capture of stochastic defects, high aspect ratio features in the front and back end of line and overlay accuracy which stem from optical 3D effects. The solution will serve the most advanced fabs worldwide for high-volume manufacturing of next generation logic and memory devices.
In process integration beyond state of the art relates to process development for Gate All Around Nanosheet devices, including inner spacers, ‘zero thickness’ Work Function Metal shifters for Replacement Metal Gate, in-situ doped S/D and heavy metals silicide for contacts. For MOL, Buried Power Rail for logic cell area scaling. For BEOL, self-aligned Via for semi-damascene, Ru interconnects and air gap for RC delay reduction, and Super Via for interconnect congestion reduction.
PIn3S shall push mask repair towards the 3nm node performance which is well beyond the present state of the art. To achieve this, a mask repair tool prototype system including a novel repair-specific-aberration-corrected E-beam column was developed and built. Repair etches demonstrated a mask repair resolution in line with the 3nm node mask repair requirements. Additionally, repair success was validated for a Process-Of-Record POR EUV test mask with programmed defects using SEM and aerial image measurements (AIMS). Furthermore, Artificial Intelligence was used for the first time in a mask defect- and repair assessment tool showing a 100% defect detection rate for several mask pattern types. Finally, the mask sample analysis technology has been extended by combining SEM-FIB-EDX mask sample measurements with AFM and TEM data.
In metrology progress beyond state of the art includes new generation of metrology and inspection tools which will be ready for the 3nm technology node challenges such as to maximize the capture of stochastic defects, high aspect ratio features in the front and back end of line and overlay accuracy which stem from optical 3D effects. The solution will serve the most advanced fabs worldwide for high-volume manufacturing of next generation logic and memory devices.
In process integration beyond state of the art relates to process development for Gate All Around Nanosheet devices, including inner spacers, ‘zero thickness’ Work Function Metal shifters for Replacement Metal Gate, in-situ doped S/D and heavy metals silicide for contacts. For MOL, Buried Power Rail for logic cell area scaling. For BEOL, self-aligned Via for semi-damascene, Ru interconnects and air gap for RC delay reduction, and Super Via for interconnect congestion reduction.