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Integrated Qubits Towards Future High-Temperature Silicon Quantum Computing Hardware Technologies

Project description

Building quantum computing hardware that can operate at higher cryogenic temperatures

Quantum technologies have the potential to solve computational problems that are too complex for classical computers. Current hardware quantum technologies are primarily limited to integrated qubits that operate at extreme cryogenic temperatures measuring tens to hundreds millikelvin. The control and readout circuits are also external to the chip containing the qubits. Put together, all these issues act as barriers to building practical quantum computers with a large number of qubits. The EU-funded IQubits project plans to develop integrated qubit control and readout circuits that can operate at higher temperatures and can be integrated together onto the same chip. In particular, researchers will develop high-temperature Si and SiGe hole–spin qubits and integrated circuits in commercial 22 nm fully depleted silicon-on-insulator CMOS technology.

Objective

The objectives of the interdisciplinary project IQubits are to (i) develop and demonstrate experimentally high-temperature (high-T) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm Fully-Depleted Silicon-on-Insulator (FDSOI) CMOS foundry technology as the enabling fundamental building blocks of quantum computing technologies, (ii) verify the scalability of these qubits to 10nm dimensions through fabrication experiments and (iii) prove through atomistic simulations that, at 2nm dimensions, they are suitable for 300K operation. The proposed 22nm FDSOI qubit ICs consist of coupled quantum-dot electron and hole spin qubits, placed in the atomic-scale channel of multi-gate n- and p-MOSFETs, and of 60-240GHz spin control/readout circuits integrated on the same die in state-of-the-art FDSOI CMOS foundry technology. To assess the impact of future CMOS scaling, more aggressively scaled Si-channel SOI and nitride-channel qubit structures will also be designed and fabricated in two experimental processes with 10nm gate half pitch. The latter will be developed in this project. The plan is for the III-nitrides (III-N) qubits to be ultimately grown on a SOI wafer, to be compatible with CMOS. Because of their larger bandgap, III-N hold a better prospect than Si and SiGe for qubits with larger coupling energy and mode energy splitting, and 300K operation. As a radical breakthrough, the fabricated qubits will feature coupling energies on the order of 0.25-1 meV corresponding to control frequencies in the 60-240GHz range, suitable for operation at 3–12 degrees Kelvin, two orders of magnitude higher than today's qubits. The tuned mm-wave circuits allow for 10-20ps spin control pulses which help to filter out wideband thermal noise and largely enhance the ratio between the gating and the decoherence times. Thermal noise filtering and fast control of the spin may lead to even higher temperature operation for a given energy-level splitting.

Call for proposal

H2020-FETOPEN-2018-2020

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Sub call

H2020-FETOPEN-2018-2019-2020-01

Coordinator

AKADEMIA GORNICZO-HUTNICZA IM. STANISLAWA STASZICA W KRAKOWIE
Net EU contribution
€ 386 505,55
Address
AL ADAMA MICKIEWICZA 30
30-059 Krakow
Poland

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Region
Makroregion południowy Małopolskie Miasto Kraków
Activity type
Higher or Secondary Education Establishments
Links
Total cost
€ 386 505,55

Participants (7)