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Integrated Qubits Towards Future High-Temperature Silicon Quantum Computing Hardware Technologies

Descrizione del progetto

DEENESFRITPL

Costruire un hardware di calcolo quantistico che possa operare a temperature criogeniche più elevate

Le tecnologie quantistiche hanno le potenzialità per risolvere problemi di calcolo troppo complessi per i computer classici. Le attuali tecnologie quantistiche hardware sono principalmente limitate a qubit integrati che operano a temperature criogeniche estreme, da decine fino a centinaia di millikelvin. I circuiti di controllo e lettura sono inoltre esterni rispetto al chip che contiene i qubit. Sommate, tutte queste problematiche rappresentano un ostacolo alla costruzione di computer quantici pratici con un grande numero di qubit. Il progetto IQubits, finanziato dall’UE, intende sviluppare circuiti integrati di controllo e lettura qubit che possono operare a temperature più elevate ed essere integrati insieme sullo stesso chip. In particolare, i ricercatori svilupperanno qubit con spin delle lacune Si e SiGe e circuiti integrati in una tecnologia CMOS commerciale di silicio su isolante interamente esaurita e da 22 nm.

Obiettivo

The objectives of the interdisciplinary project IQubits are to (i) develop and demonstrate experimentally high-temperature (high-T) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm Fully-Depleted Silicon-on-Insulator (FDSOI) CMOS foundry technology as the enabling fundamental building blocks of quantum computing technologies, (ii) verify the scalability of these qubits to 10nm dimensions through fabrication experiments and (iii) prove through atomistic simulations that, at 2nm dimensions, they are suitable for 300K operation. The proposed 22nm FDSOI qubit ICs consist of coupled quantum-dot electron and hole spin qubits, placed in the atomic-scale channel of multi-gate n- and p-MOSFETs, and of 60-240GHz spin control/readout circuits integrated on the same die in state-of-the-art FDSOI CMOS foundry technology. To assess the impact of future CMOS scaling, more aggressively scaled Si-channel SOI and nitride-channel qubit structures will also be designed and fabricated in two experimental processes with 10nm gate half pitch. The latter will be developed in this project. The plan is for the III-nitrides (III-N) qubits to be ultimately grown on a SOI wafer, to be compatible with CMOS. Because of their larger bandgap, III-N hold a better prospect than Si and SiGe for qubits with larger coupling energy and mode energy splitting, and 300K operation. As a radical breakthrough, the fabricated qubits will feature coupling energies on the order of 0.25-1 meV corresponding to control frequencies in the 60-240GHz range, suitable for operation at 3–12 degrees Kelvin, two orders of magnitude higher than today's qubits. The tuned mm-wave circuits allow for 10-20ps spin control pulses which help to filter out wideband thermal noise and largely enhance the ratio between the gating and the decoherence times. Thermal noise filtering and fast control of the spin may lead to even higher temperature operation for a given energy-level splitting.

Campo scientifico

Programma(i)

Argomento(i)

Invito a presentare proposte

H2020-FETOPEN-2018-2020

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Bando secondario

H2020-FETOPEN-2018-2019-2020-01

Meccanismo di finanziamento

RIA - Research and Innovation action

Coordinatore

AARHUS UNIVERSITET
Contribution nette de l'UE
€ 788 625,00
Indirizzo
Nordre ringgade 1
8000 Aarhus c
Danimarca

Mostra sulla mappa
Regione
Danmark Midtjylland Østjylland
Tipo di attività
Higher or Secondary Education Establishments
Collegamenti
Altri finanziamenti
€ 143 622,50

Partecipanti (6)

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Ultimo aggiornamento: 24 Maggio 2022

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Permalink: https://cordis.europa.eu/project/id/829005/it

European Union, 2023