Design margins are necessary to ensure reliable operation of integrated circuits over extreme ranges of manufacturing Process variations and environmental variations (Voltage, Temperature). On top of these PVT variations, aging related parametric drift (e.g. due to Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) and Electromigration (EM)) also limits performance by requiring additional timing margin. Design-for-worst case scenario or so-called “corner-based design” methodology can be a potential solution. However, this approach is sub-optimal, because it applies margins which are in practice, either too optimistic or pessimistic since it ignores the correlation effects which exist inherently due to the circuit topology and the realistic application workload effects. The goal of this project is to address runtime tradeoffs associated with considering real workloads during chip design. A workload-dependent reliability aware optimization flow under the influence of BTI aging has been proposed by utilizing an optimal margining scheme. The proposed flow considers the relevant correlations in a design by modelling the degradation much more accurately and thus it enables achieving the desired quality-of-service and reliability specifications while clearly improving the Power-Performance-Area (PPA) overheads.
As planned, the project duration was 24 months and during this period, ABSREF has been able to address most of the sub-objectives and achieve the set goals under corresponding work packages (WP). It is worth mentioning that the sub-objectives defined under WP3 were achieved with development of two separate simulation flows instead of one, as anticipated in the beginning of the project. The first flow was dedicated to assessment of aging under realistic workload scenarios by use of aging aware timing libraries. The second flow was based on using aging-aware timing degradation of standard cells; suitable for design optimization in order to achieve target specifications. Both these flows can be deployed in industry standard EDA tool flows to do aging assessment and optimization depending on the need. Considering the vastness and complexity of the physics behind the different types of aging mechanisms like, BTI, HCI and EM, the project was carried out starting with Negative BTI (NBTI) which is the most important front end of line (FEOL) degradation mechanism affecting the P-channel metal–oxide–semiconductor (PMOS) transistors. However, the developed framework is still capable of handling HCI with minor modification to the flow. This exercise is currently being actively undertaken within the host organisation, IMEC. The mechanism which mostly affects the back end of line (BEOL) wire reliability is EM. Even though, in principle the framework can be applied to EM, the flow implementation has been kept out of scope of this project. This is because of the current unavailability of a suitable physics-based model to capture the transient effects due to various workloads.
The following project objectives have been addressed:
I. System level architecture & microarchitecture emulation [WP1]
II. RTL synthesis, mapping and gate level simulations [WP1]
III. Developing efficient compression algorithm [WP2]
IV. Evaluation of aging degradation due to short-term use and extrapolation to long-term usage [WP2]
V. Performing workload dependent standard cell library characterization [WP3]
VI. Static Timing Analysis (STA) and logic optimization [WP3]
VII. Place &route and post-layout timing analysis [WP3]
