Project description
New on-chip wireless communication plane
Future wireless communication systems and computing platforms need to deliver much higher data rates, more flexibility, and a significantly higher energy efficiency than current systems. As heterogeneous processors are widely available, new platforms are required to leverage a huge amount of computing power. To ensure near-ASIC (application-specific integrated circuit) efficiency without the cost, development time or limitations, the EU-funded WiPLASH project is developing an on-chip wireless communication plane to provide architectural plasticity, reconfigurability and adaptation for any application requirements without any loss of generality. Specifically, the project will design a miniaturised and tuneable graphene antenna prototype in the terahertz band. It will also co-integrate graphene RF components with submillimetre-wave transceivers and demonstrate low-power reconfigurable wireless chip-scale networks.
Objective
The main design principles in computer architecture have shifted from a monolithic scaling-driven approach towards an emergence of heterogeneous architectures that tightly co-integrate multiple specialized computing and memory units. This is motivated by the urgent need of very high parallelism and by energy constraints. This heterogeneous hardware specialization requires interconnection mechanisms that integrate the architecture. State-of-the-art approaches are 3D stacking and 2.D architectures complemented with a Network-on-Chip (NoC) to interconnect the components. However, such interconnects are fundamentally monolithic and rigid, and are unable to provide the efficiency and architectural flexibility required by current and future key ICT applications. The main challenge is to introduce diversification and specialization in heterogeneous processor architectures while ensuring their generality and scalability.
In order to achieve this, the WiPLASH project aims to pioneer an on-chip wireless communication plane able to provide architectural plasticity, reconfigurability and adaptation to the application requirements with near-ASIC efficiency but without any loss of generality. For this, the WiPLASH consortium will provide solid experimental foundations of the key enablers of on-chip wireless communication at the functional unit level as well as their technological and architectural integration. The main goals are: (i) prototype a miniaturized and tunable graphene antenna in the terahertz band, (ii) co-integrate graphene RF components with submillimeter-wave transceivers and (iii) demonstrate low-power reconfigurable wireless chip-scale networks. The culminating goal is to demonstrate that the wireless plane offers the plasticity required by future computing platforms by improving at least one key application (mainly biologically-plausible deep learning architectures) by 10X in terms of execution speed and energy-delay product over a state-of-the-art baseline.
Fields of science
- engineering and technologynanotechnologynano-materialstwo-dimensional nanostructuresgraphene
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringanalogue electronics
- natural sciencescomputer and information sciencesartificial intelligencemachine learningdeep learning
- engineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsradio technology
Keywords
Programme(s)
Funding Scheme
RIA - Research and Innovation actionCoordinator
08034 Barcelona
Spain