Periodic Reporting for period 2 - ANDANTE (Ai for New Devices And Technologies at the Edge)
Período documentado: 2021-05-01 hasta 2022-05-31
The strong increase of IoT systems deployment in many applications areas and the enormous amount of data generated (Big data) requires efficient data analysis tools and techniques. AI/ML/DL is becoming a first solution of choice and implemented to run in the cloud. However, this system architecture solution is inefficient because the data analysis and processing is fare a way from the data sources bringing the following inconveniences:
- Use of huge amount of natural resources : electricity and water(for cooling) for the data centers operation.
- Use of huge communication resources (bandwidth), which increase the power consumption, the latency (avoiding the development of real-time applications), the surface attacks for cyber-security threads and consequently risks to not ensure a good privacy level.
- Use of huge amount of memory.
Cloud computing solutions are not adapted or inefficient for many applications that could run much more efficiently in the EDGE.
ANDANTE aims at developing technology solutions allowing efficient data analysis in the edge instead of in the cloud and contributes to eliminate the cloud computing drawbacks and consequently contributes in the sustainability of the new Edge base applications using embedded AI/ML/DL techniques. For instance by
- Reducing the natural resources use such electricity and water consumption
- Reducing the use of communication bandwidth and its impact in power consumption
- Allowing the development of real-time application thanks to a low latency solutions.
- Reducing the memory print and its impact of reduce power consumption in the overall system.
- Increasing the security and privacy level
- Increasing and allowing more intelligent IoT solutions in many areas such ad Digital Industry, Digital Farming, Transport and Smart Mobility, Healthcare and Digital Life.
To contribute to get all these benefits, ANDANTE goals are the following:
- To create the AI/ML/DL foundations for future products in the edge IoT domain
- To leverage innovative IC (Integrated circuits) accelerators based on artificial and spiking neural networks to build strong hardware and software platforms for application developments.
- To combine extreme power efficiency with robust neuromorphic computing capabilities for the resulting IoT devices
- To achieve efficient cross-fertilization between major European foundries, chip designers, system houses, application companies, RTOs and academic research partners.
- To build and expand the European ecosystem around the definition, development, production and application of neuromorphic ICs.
- To promote innovative hardware and software deep-learning solutions for future IoT at the edge products that combine extreme power efficiency, robust and powerful cognitive computing capabilities.
- Use of huge amount of natural resources : electricity and water(for cooling) for the data centers operation.
- Use of huge communication resources (bandwidth), which increase the power consumption, the latency (avoiding the development of real-time applications), the surface attacks for cyber-security threads and consequently risks to not ensure a good privacy level.
- Use of huge amount of memory.
Cloud computing solutions are not adapted or inefficient for many applications that could run much more efficiently in the EDGE.
ANDANTE aims at developing technology solutions allowing efficient data analysis in the edge instead of in the cloud and contributes to eliminate the cloud computing drawbacks and consequently contributes in the sustainability of the new Edge base applications using embedded AI/ML/DL techniques. For instance by
- Reducing the natural resources use such electricity and water consumption
- Reducing the use of communication bandwidth and its impact in power consumption
- Allowing the development of real-time application thanks to a low latency solutions.
- Reducing the memory print and its impact of reduce power consumption in the overall system.
- Increasing the security and privacy level
- Increasing and allowing more intelligent IoT solutions in many areas such ad Digital Industry, Digital Farming, Transport and Smart Mobility, Healthcare and Digital Life.
To contribute to get all these benefits, ANDANTE goals are the following:
- To create the AI/ML/DL foundations for future products in the edge IoT domain
- To leverage innovative IC (Integrated circuits) accelerators based on artificial and spiking neural networks to build strong hardware and software platforms for application developments.
- To combine extreme power efficiency with robust neuromorphic computing capabilities for the resulting IoT devices
- To achieve efficient cross-fertilization between major European foundries, chip designers, system houses, application companies, RTOs and academic research partners.
- To build and expand the European ecosystem around the definition, development, production and application of neuromorphic ICs.
- To promote innovative hardware and software deep-learning solutions for future IoT at the edge products that combine extreme power efficiency, robust and powerful cognitive computing capabilities.
First Period:
WP6 Management
- The project has been set up: Rules and procedures for Consortium and WPs collaboration were set up, and risk management done
- The Collaboration infrastructure based in SharePoint was point in place:
- Project dissemination and visibility: Website set up and first Newsletter published
WP1:
- Use cases requirements were defined
- Use cases system specifications on going
WP2:
- Scorecard for eNVM target specs for ANN and SNN report available in draft version
- Cell layouts for PCM, OxRAM, SOT-MRAM, FeFET, TFT report available
WP3
- Tools and methodologies specifications defined and Tools under development
- Building blocks specifications on going
- Foundation IPs specifications on going
WP4
- ASIC requirements and specifications on going
- Platforms requirements on going
WP5
- Use case specifications on going
Second Period:
WP6 Management
- Project management and reporting
- Project dissemination and visibility: Increase the dissemination through articles, workshop and conferences
- Preparation of the first draft plan for use and dissemination of results
WP1:
- Use cases requirements were defined
- Use cases system specifications were completed.
- Monitoring of use cases requirements vs implementation
- WP1 achieved, but the monitoring that it is foreseen till project end.
WP2:
- Morphology validation for PCM and OxRAM completed
- Bitcell level device and selector integration (for OxRAM, PCRAM, MRAM, FeFET, selector material development and integration for OxRAM and PCRAM) done
WP3
- Tools and methodologies specifications defined
- Tools and methodologies implementation, 16 different tools have been developed.
- Building blocks specifications completed
- Foundation IPs specifications completed
- Foundation IPs implementation has been delayed, mainly due technology change, for instance from ST 28FDSOI to GF 22FDX
This technology change has caused a delay in the project of 6 months and impacting the WP4 and WP5
- 6 FPGAs are being designed in this WP3
WP4
- ASIC requirements and specifications completed
- Platforms requirements and specifications completed
- Architectural design of the ASICs completed
- Design and implementation of ASICs on going
- The original SNN ASIC 1.2 has been redefined to make a design using ST P18 technology with PCM instead of ST28 FDSOI.
WP5
- Use case specifications of the 5 application domains were completed.
- Use case development is on going
WP6 Management
- The project has been set up: Rules and procedures for Consortium and WPs collaboration were set up, and risk management done
- The Collaboration infrastructure based in SharePoint was point in place:
- Project dissemination and visibility: Website set up and first Newsletter published
WP1:
- Use cases requirements were defined
- Use cases system specifications on going
WP2:
- Scorecard for eNVM target specs for ANN and SNN report available in draft version
- Cell layouts for PCM, OxRAM, SOT-MRAM, FeFET, TFT report available
WP3
- Tools and methodologies specifications defined and Tools under development
- Building blocks specifications on going
- Foundation IPs specifications on going
WP4
- ASIC requirements and specifications on going
- Platforms requirements on going
WP5
- Use case specifications on going
Second Period:
WP6 Management
- Project management and reporting
- Project dissemination and visibility: Increase the dissemination through articles, workshop and conferences
- Preparation of the first draft plan for use and dissemination of results
WP1:
- Use cases requirements were defined
- Use cases system specifications were completed.
- Monitoring of use cases requirements vs implementation
- WP1 achieved, but the monitoring that it is foreseen till project end.
WP2:
- Morphology validation for PCM and OxRAM completed
- Bitcell level device and selector integration (for OxRAM, PCRAM, MRAM, FeFET, selector material development and integration for OxRAM and PCRAM) done
WP3
- Tools and methodologies specifications defined
- Tools and methodologies implementation, 16 different tools have been developed.
- Building blocks specifications completed
- Foundation IPs specifications completed
- Foundation IPs implementation has been delayed, mainly due technology change, for instance from ST 28FDSOI to GF 22FDX
This technology change has caused a delay in the project of 6 months and impacting the WP4 and WP5
- 6 FPGAs are being designed in this WP3
WP4
- ASIC requirements and specifications completed
- Platforms requirements and specifications completed
- Architectural design of the ASICs completed
- Design and implementation of ASICs on going
- The original SNN ASIC 1.2 has been redefined to make a design using ST P18 technology with PCM instead of ST28 FDSOI.
WP5
- Use case specifications of the 5 application domains were completed.
- Use case development is on going
Multi-core SNN devices with optmizied event-based routing schemes do not exist yet. So far architectures such as SpiNNaKer and Loihi implement general purpose routing schemes, trading off efficiency (in terms of power, bandwidth, and latency) versus programmability. As we already know we will be targeting very specific edge-computing use cases we can customize the routing scheme design to these applications. We expect the final device to be significantly faster and lower-power than the current state-of-the-art.