First Period:
WP1: Use cases requirements and system specifications defined
WP2: 2 deliverables were produced: Scorecard for completed target specs for ANN and SNN, and Cell layouts for PCM, SOT-MRAM, FeFET, TFT
WP3: The specifications for Tools and methodologies, building blocks, and Foundation IPs defined
WP4: The ASIC and platform requirements defined
WP5: Use case specifications defined
WP6 Management: the project was set up: Rules and procedures for Consortium and WPs collaboration and risk management, collaboration infrastructure based in SharePoint, the Website, and first Newsletter published
Second Period:
WP1: Use cases and system requirements completed
WP2: Morphology validation for PCM and OxRAM completed. Bitcell level device and selector integration completed
WP3: The development of 17 different tools completed. 6 FPGAs were designed
WP4: The ASICS requirements, specifications and architectural design completed. The original SNN ASIC 1.2 redefined for a design in ST P18 technology
WP5: Use case specifications of the 5 application domains completed and developments ongoing
WP6: Project management, reporting and dissemination done
Third Period
The major activities and achievements in line with the objectives and activities initially planned
WP1: Tracking of the 14 use cases and their 19 associated demonstrators to ensure alignment between the use case system specifications and their implementation
WP2: Full flow lots for the 40 nm SOT-MRAM, 28nm FDSOI and 22 FDX technologies available and three other technologies (PCM, 2T1C backend DRAM, and IGZO-based FeTFT) were implemented with the aim of creating multi-level cells – closer to analog behavior. Devices were successfully characterized
WP3: The design of ASICS, SoCs and FPGAs followed different implementation strategies. 17 tools were upgraded for training, HW generation, neural network mapping on HW, and simulation. Moreover, 6 FPGA accelerators and associated algorithms and models were achieved. The design of analog in-memory computing IPS and macro-block of neural network were developed and fabricated to exploit the capabilities of embedded NVM technologies
WP4: 6 ASICs (3 SNN, 1 Front end, 2 ANN) and 2 SoCs were designed, fabricated, validated, and characterized. 4 platforms and one board are functional. The resulting neuromorphic processors are very efficient with very low energy consumption on the order of uW for SNN ASICs, few mW for ANN ASICs and several hundred mW for the AI SoCs
WP5: 19 demonstrators across 14 use cases in 5 application domains including gathering additional data, developing AI models, implementing non-AI software components. Moreover, reference implementations and simulations were realized, and all these setups were used to evaluate the ANDANTE results
WP6: Dissemination and promotion of the ANDANTE results: 4 Thesis, 45 Patents, 4 Chapters/Books, 18 Scientific publications in Journals, 32 Scientific publications in conferences, 50 Presentations in conferences and workshops, 5 Workshops organized by ANDANTE, 5 Technical fairs and conferences, 2 Videos
