Periodic Reporting for period 1 - SecuReHLS (EDA tools for Secure and Reliable High Level Synthesis Implementations)
Período documentado: 2020-09-01 hasta 2022-08-31
In our increasingly digital world, System-on-Chip (SoC) and Internet-of-Things (IoT) technologies are becoming fundamental to enhancing many aspects of daily life, from smart homes and cities to healthcare and automotive applications. These technologies, integrating computational units, sensors, and network capabilities, have the potential to significantly improve our interaction with the surrounding environment by processing and communicating sensitive information. However, the rapid adoption of SoC and IoT devices raises substantial security and reliability concerns. Ensuring the trustworthiness of these devices in handling sensitive data and operating reliably, even in harsh conditions, is imperative for user privacy and safety.
The main issue addressed by this project revolves around developing methodologies to concurrently enhance the security and reliability of SoC and IoT devices. Given the critical nature of these devices, it's essential to protect them from both hardware attacks, such as Fault Injection (FI) and Side Channel Analysis (SCA), and environmental threats that could lead to system failures. These challenges are paramount, considering that SoC and IoT devices increasingly process sensitive information and are deployed in scenarios where security breaches or reliability failures could have serious consequences.
The project's primary objective was to develop advanced methodologies and algorithms that could be integrated into High-Level Synthesis (HLS) flows used for designing hardware accelerators. These methodologies aim to assess and improve the security and reliability of SoC and IoT devices. The focus was particularly on devices utilizing FPGA technology, due to its flexibility and widespread use in creating specialized computing solutions.
In conclusion, the project made important steps towards creating safer and more reliable digital infrastructures. By addressing the dual challenges of security and reliability in SoC and IoT devices, this research contributes towards the deployment of advanced technologies that align with societal expectations for privacy, safety, and trust.
The main issue addressed by this project revolves around developing methodologies to concurrently enhance the security and reliability of SoC and IoT devices. Given the critical nature of these devices, it's essential to protect them from both hardware attacks, such as Fault Injection (FI) and Side Channel Analysis (SCA), and environmental threats that could lead to system failures. These challenges are paramount, considering that SoC and IoT devices increasingly process sensitive information and are deployed in scenarios where security breaches or reliability failures could have serious consequences.
The project's primary objective was to develop advanced methodologies and algorithms that could be integrated into High-Level Synthesis (HLS) flows used for designing hardware accelerators. These methodologies aim to assess and improve the security and reliability of SoC and IoT devices. The focus was particularly on devices utilizing FPGA technology, due to its flexibility and widespread use in creating specialized computing solutions.
In conclusion, the project made important steps towards creating safer and more reliable digital infrastructures. By addressing the dual challenges of security and reliability in SoC and IoT devices, this research contributes towards the deployment of advanced technologies that align with societal expectations for privacy, safety, and trust.
One of the key achievements of the project was the creation of open-source tools to study the security and reliability levels of HLS implementations, making it easier for other researchers and companies to conduct their own evaluations. The tools cover a range of evaluation needs, from simulating fault injection scenarios to analyzing potential side-channel attacks.
We developed several hardware accelerators to test the vulnerability of these systems to Fault Injection (FI) and Side Channel Analysis (SCA) attacks. This work led to identify critical vulnerabilities caused by the HLS tools and provided a foundation for enhancing security and reliability. Then, we proposed countermeasures against: a) SCA and b) FI. For each benchmark, multiple syntheses were performed using different sets of HLS directives and extensive evaluations of the protected accelerators were conducted to reveal security and reliability pitfalls due to HLS.
One of the main advantages of HLS is the fact that it can generate huge amounts of different RTL designs. A major drawback of security and reliability evaluation tools is that due to the large time to complete a thorough evaluation, developers cannot afford time-wise to evaluate many implementations generated by HLS tools. Since the evaluations are time consuming, the design space exploration allowed by HLS tools is not feasible. We address this issue by employing state of the art Machine Learning techniques based on Graph Neural Networks (GNN). The proposed GNN-based framework can be trained through a set of RTL netlists generated by the HLS flow (which are represented by graphs) and then accurately and rapidly predict the reliability level (i.e. error rates) of new graphs (i.e. designs).
Moreover, to automate the protections during HLS, we introduced a novel scheduling algorithm based on Force Directed Scheduling (FDS). This algorithm minimizes operational and register overlap between redundant modules, enhancing the security resilience of the design against fault injection attacks without compromising on design metrics significantly. The experimental results showed that our approach could dramatically reduce critical errors while maintaining acceptable overheads in latency, area, and power consumption.
The results have been shared with the wider research community and hold potential for adoption by industry partners, contributing to the development of more secure and reliable digital technologies. The project's findings have been disseminated the following publications: DFTS2021, DFTS2023, IOLTS2022, DATE2024. Notably, one of our papers received the Best Paper Award at the DFT 2023 conference. In addition to these conference proceedings, two journal articles have been submitted for publication, further expanding the reach and impact of our research findings.
We developed several hardware accelerators to test the vulnerability of these systems to Fault Injection (FI) and Side Channel Analysis (SCA) attacks. This work led to identify critical vulnerabilities caused by the HLS tools and provided a foundation for enhancing security and reliability. Then, we proposed countermeasures against: a) SCA and b) FI. For each benchmark, multiple syntheses were performed using different sets of HLS directives and extensive evaluations of the protected accelerators were conducted to reveal security and reliability pitfalls due to HLS.
One of the main advantages of HLS is the fact that it can generate huge amounts of different RTL designs. A major drawback of security and reliability evaluation tools is that due to the large time to complete a thorough evaluation, developers cannot afford time-wise to evaluate many implementations generated by HLS tools. Since the evaluations are time consuming, the design space exploration allowed by HLS tools is not feasible. We address this issue by employing state of the art Machine Learning techniques based on Graph Neural Networks (GNN). The proposed GNN-based framework can be trained through a set of RTL netlists generated by the HLS flow (which are represented by graphs) and then accurately and rapidly predict the reliability level (i.e. error rates) of new graphs (i.e. designs).
Moreover, to automate the protections during HLS, we introduced a novel scheduling algorithm based on Force Directed Scheduling (FDS). This algorithm minimizes operational and register overlap between redundant modules, enhancing the security resilience of the design against fault injection attacks without compromising on design metrics significantly. The experimental results showed that our approach could dramatically reduce critical errors while maintaining acceptable overheads in latency, area, and power consumption.
The results have been shared with the wider research community and hold potential for adoption by industry partners, contributing to the development of more secure and reliable digital technologies. The project's findings have been disseminated the following publications: DFTS2021, DFTS2023, IOLTS2022, DATE2024. Notably, one of our papers received the Best Paper Award at the DFT 2023 conference. In addition to these conference proceedings, two journal articles have been submitted for publication, further expanding the reach and impact of our research findings.
The project represents a significant leap beyond the current state of the art in the security and reliability of hardware accelerators, particularly those used in System-on-Chip (SoC) and Internet-of-Things (IoT) technologies. Through the development of innovative evaluation tools and methodologies, along with the automation of security and reliability enhancements in the High-Level Synthesis (HLS) design flow, the project is contributing towards the design and deployment of secure and reliable digital infrastructure.
The introduction of tools capable of evaluating and mitigating fault injection and side-channel attacks addresses the growing concerns around the vulnerability of hardware accelerators to hardware attacks. Additionally, the use of Graph Neural Networks (GNN) for predicting hardware security properties represents an important application of machine learning techniques to the field of hardware security, offering efficient means of evaluating potential vulnerabilities. The project's approach to automating the incorporation of redundancy based countermeasures development of the Secure Scheduling and automated protecting algorithms for security purposes form novel contributions.
By enhancing the security and reliability of SoC and IoT devices, the project contributes to the trustworthiness and resilience of critical digital infrastructure and devices. This is particularly relevant in applications where the integrity and availability of data are paramount, such as in healthcare, automotive, and financial services. Improved security and reliability not only protect against economic losses due to data breaches and system failures but also safeguard human lives by ensuring the dependability of critical application.
As digital technologies become more embedded in everyday life, the public's trust in these technologies becomes crucial. By advancing the state of the art in hardware security and reliability, the project helps to foster a safer digital environment, encouraging the adoption of digital solutions. Furthermore, the project's contributions to the academic communities, stimulate ongoing innovation in the field, ensuring that the benefits of this research extend beyond the project's duration.
In summary, the project not only pushes the boundaries of current technology but also lays the groundwork for more secure and reliable digital systems, with far-reaching benefits for society at large.
The introduction of tools capable of evaluating and mitigating fault injection and side-channel attacks addresses the growing concerns around the vulnerability of hardware accelerators to hardware attacks. Additionally, the use of Graph Neural Networks (GNN) for predicting hardware security properties represents an important application of machine learning techniques to the field of hardware security, offering efficient means of evaluating potential vulnerabilities. The project's approach to automating the incorporation of redundancy based countermeasures development of the Secure Scheduling and automated protecting algorithms for security purposes form novel contributions.
By enhancing the security and reliability of SoC and IoT devices, the project contributes to the trustworthiness and resilience of critical digital infrastructure and devices. This is particularly relevant in applications where the integrity and availability of data are paramount, such as in healthcare, automotive, and financial services. Improved security and reliability not only protect against economic losses due to data breaches and system failures but also safeguard human lives by ensuring the dependability of critical application.
As digital technologies become more embedded in everyday life, the public's trust in these technologies becomes crucial. By advancing the state of the art in hardware security and reliability, the project helps to foster a safer digital environment, encouraging the adoption of digital solutions. Furthermore, the project's contributions to the academic communities, stimulate ongoing innovation in the field, ensuring that the benefits of this research extend beyond the project's duration.
In summary, the project not only pushes the boundaries of current technology but also lays the groundwork for more secure and reliable digital systems, with far-reaching benefits for society at large.