Periodic Reporting for period 1 - SHADE (Spin Hall-Based Analog to Digital Encoder for Ultra-Compact Sensor Nodes)
Berichtszeitraum: 2020-08-01 bis 2022-07-31
Analog to digital converter (ADC)S that translate analog data to digital data play a crucial role in most computational systems. With emerging new applications such as deep learning (DL), the internet of things (IoT), and computing in memory (CiM), the need for compact and low-power ADC is increasing. Conventional ADCs like other analog circuits suffer from the difficulty of scaling because of the large process variation and low supply voltage. According to the recent roadmap prediction of ADC reports that the ADC performance shows no obvious improvement in the resolution, area, and power consumption in the next 10 years using the current technology. One promising solution can be moving from conventional complementary metal-oxide-semiconductor (CMOS) technology to new hybrid technologies. To this end, new technologies such as spintronics, which are compatible with complementary metal-oxide-semiconductor (CMOS) technology can be strongly considered.
The overall aim of (10.1109/TED.2022.3142649) [1], was to implement ADCs based on the SH-MTJ in order to improve the compactness and power consumption of the current ADCs. In(10.1088/1361-6641/ac419c) the proof-of-concept of the implementation of the proposed quantizer in(10.1109/TED.2022.314264) as a synapse in neuromorphic computing has been investigated. Because the proposed multi-state SOT synapse can solve the state-limited issue of spin-based synapses.
[1] H. Ghanatian et al, “A Hybrid Spin-CMOS Flash ADC based on Spin Hall Effect and Spin Transfer Torque, ” accepted in 40th IEEE International Conference on Computer Design (ICCD).
[2]H. Ghanatian et al“Spin-CMOS Flash ADC based on spin-orbit-torque,” Scientific Reports.
The overall aim of (10.1109/TED.2022.3142649) [1], was to implement ADCs based on the SH-MTJ in order to improve the compactness and power consumption of the current ADCs. In(10.1088/1361-6641/ac419c) the proof-of-concept of the implementation of the proposed quantizer in(10.1109/TED.2022.314264) as a synapse in neuromorphic computing has been investigated. Because the proposed multi-state SOT synapse can solve the state-limited issue of spin-based synapses.
[1] H. Ghanatian et al, “A Hybrid Spin-CMOS Flash ADC based on Spin Hall Effect and Spin Transfer Torque, ” accepted in 40th IEEE International Conference on Computer Design (ICCD).
[2]H. Ghanatian et al“Spin-CMOS Flash ADC based on spin-orbit-torque,” Scientific Reports.
In (10.1109/TED.2022.314264) a 3-bit Flash spin-orbit torque analog to digital converter (SOT-ADC) is presented which works based on switching of a perpendicular-anisotropy magnetic tunnel junction (p-MTJ) by spin Hall effect (SHE) assisted by spin-transfer torque (STT). To quantize the input signal into 8 states, a heavy metal (HM) with different cross-sectional areas that is shared with seven MTJs is utilized. To enable deterministic switching, STT currents are employed. However, such currents make challenges during the conversion and sensing phases which are addressed in this work (Fig.1).
In [1], a 3-bit hybrid spin-CMOS Flash ADC is developed in which the structure consists of unconnected p-MTJs (Fig. 2). In this structure, a copy of the input current (Iin) passes through the HM of each p-MTJ, which improves the tunnel magnetoresistance (TMR) and as a result increasing the reading reliability, linearity, and speed of spin Hall-based ADCs with attached HMs.
In [2], In this paper, the proof-of-concept of the ADC implementation by spintronic devices is investigated and provides design guidelines for future spin-CMOS ADCs. To this end, in-plane-anisotropy magnetic tunnel junctions (i-MTJs) that are switched based on spin-orbit torque (SOT), are designed, fabricated, and characterized to implement a 3-bit hybrid spin-CMOS Flash ADC. The ADC consists of 7 unconnected i-MTJs with different HM widths.
In (10.1088/1361-6641/ac419c) the peripheral circuits of the implementation of the STDP have been designed (Fig. 3).
In [1], a 3-bit hybrid spin-CMOS Flash ADC is developed in which the structure consists of unconnected p-MTJs (Fig. 2). In this structure, a copy of the input current (Iin) passes through the HM of each p-MTJ, which improves the tunnel magnetoresistance (TMR) and as a result increasing the reading reliability, linearity, and speed of spin Hall-based ADCs with attached HMs.
In [2], In this paper, the proof-of-concept of the ADC implementation by spintronic devices is investigated and provides design guidelines for future spin-CMOS ADCs. To this end, in-plane-anisotropy magnetic tunnel junctions (i-MTJs) that are switched based on spin-orbit torque (SOT), are designed, fabricated, and characterized to implement a 3-bit hybrid spin-CMOS Flash ADC. The ADC consists of 7 unconnected i-MTJs with different HM widths.
In (10.1088/1361-6641/ac419c) the peripheral circuits of the implementation of the STDP have been designed (Fig. 3).
In (10.1109/TED.2022.314264) According to simulation results, power consumption and maximum sampling rate (including all conversion, sensing, and reset phases) of the ADC are 416 µW and 102 MS/s in 180 nm CMOS technology, respectively. In addition, the differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.258 least significant bit (LSB) and -0.275 LSB, respectively. The comparison between this work and other spin-based ADC and CMOS-based ADC is shown in Table.1.
In [1], The simulation results in 180nm CMOS technology show 845 µW of power consumption at 200 MS/s with the differential nonlinearity (DNL) and integral nonlinearity (INL) of -0.149 LSB (least significant bit) and 0.085 LSB, respectively. The comparison between this work and other spin-based ADC and CMOS-based ADC is shown in Table.2.
In [2], Based on the simulation results, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively. To this end, a behavioral model of the i-MTJs is extracted from the experimental measurement. Moreover, the effect of the process variation of MTJs and interface CMOS circuit on Is IS of MTJs is investigated by Monte Carlo simulation. The simulation results show that the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. The results are shown in Fig. 4 and Fig.5.
In (10.1088/1361-6641/ac419c) the proposed uulti-state SOT synapse can relax the bi-state synapse issue observed in MTJs and the variation of the weight versus the difference in spike times of a postsynaptic neuron (tpost) and presynaptic neuron (tpre) in Fig. 6.
In [1], The simulation results in 180nm CMOS technology show 845 µW of power consumption at 200 MS/s with the differential nonlinearity (DNL) and integral nonlinearity (INL) of -0.149 LSB (least significant bit) and 0.085 LSB, respectively. The comparison between this work and other spin-based ADC and CMOS-based ADC is shown in Table.2.
In [2], Based on the simulation results, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively. To this end, a behavioral model of the i-MTJs is extracted from the experimental measurement. Moreover, the effect of the process variation of MTJs and interface CMOS circuit on Is IS of MTJs is investigated by Monte Carlo simulation. The simulation results show that the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. The results are shown in Fig. 4 and Fig.5.
In (10.1088/1361-6641/ac419c) the proposed uulti-state SOT synapse can relax the bi-state synapse issue observed in MTJs and the variation of the weight versus the difference in spike times of a postsynaptic neuron (tpost) and presynaptic neuron (tpre) in Fig. 6.