Objective We will investigate how to make three-dimensional, self-aligning, molecular connections ("wires") between circuits on separate, closely spaced layers. Special test rigs will be used to measure electrical signals passing through molecular wires joining two (eventually three) layers, as a function of layer alignment and spacing. Each test chip will have a regular pattern of small conducting pads: the final version will have 2 micrometer (um) sized pads on a 25 um spacing. High density conducting connection using regularly spaced holes between both sides of a chip will also be examined.The project will provide:1. a way to improve the density of conventional semiconductor circuits,2. A way to improve long-distance connections between nanoscale processors,3. The enabling technology for a retina-cortex unit running at 10 teraOps (10[13] ops/sec) in a 25mm cube.We will investigate how to make three-dimensional, self-aligning, molecular connections ("wires") between circuits on separate, closely-spaced layers. Special test rigs will be used to measure electrical signals passing through molecular wires joining two (eventually three) layers, as a function of layer alignment and spacing. Each test chip will have a regular pattern of small conducting pads: the final version will have 2 micrometer (um) sized pads on a 25 um spacing. High density conducting connection using regularly spaced holes between both sides of a chip will also be examined.The project will provide:1. a way to improve the density of conventional semiconductor circuits,2. A way to improve long-distance connections between nano-scale processors,3. The enabling technology for a retina-cortex unit running at 10 teraOps (10[13] ops/sec) in a 25mm cube.OBJECTIVESThe long-term objective is to develop an enabling technology for three-dimensional computer structures, whether micro-, nano-, or molecular-electronic. The specific objective is to demonstrate the feasibility of very high-density, three-dimensional molecular "wires" between closely-space chips or other types of layer.The technical objectives are:1. to develop four different 3D molecular connection technologies2. to measure and compare their performance using the same test structures3. to investigate the long-term reliability of such connections4. to investigate closely-spaced through-chip connections and thinning of circuit substrates5. to determine the maximum number of devices per unit volume6. to devise computer structures using this new 3D connection technique.DESCRIPTION OF WORKWe propose a three-year programme to examine the feasibility of connecting two or more closely-spaced semiconductor layers with intercalated molecular wiring layers. Four types of molecular wire technology will be developed by three separate groups. In order to provide a common testing standard, the same type of test rig and "test chips" will be used to measure conductivity and other electrical properties as a function of the alignment and spacing between the semiconductor layers.There will be five work packages:WP1 - MOLECULAR WIRES: Design, construction and testing of molecular wires.WP2 - TEST CHIPS: Design and construction of silicon test chips and silicon, quartz or glass top-layer assemblies.WP3 - TEST RIG: Design and construction of test rigs.WP4 - ELECTRONIC LAYER FABRICATION: Investigation of factors relating to chip fabrication (wafer thinning methods, high-density through-chip connections, chemical compatibility between semiconductor and molecular elements).WP5 - THREE-D STRUCTURES: How to assemble a layered structure; fault-tolerant structures; low-power architectures. Fields of science engineering and technologymaterials engineeringnatural sciencesphysical scienceselectromagnetism and electronicssemiconductivitynatural scienceschemical sciencesinorganic chemistrymetalloids Keywords Nanotechnology Programme(s) FP5-IST - Programme for research, technological development and demonstration on a "User-friendly information society, 1998-2002" Topic(s) 1.1.2.-6.2.3 - FET P3: Nanotechnology information devices Call for proposal Data not available Funding Scheme CSC - Cost-sharing contracts Coordinator UNIVERSITY COLLEGE LONDON EU contribution No data Address GOWER STREET WC1E 6BT LONDON United Kingdom See on map Total cost No data Participants (4) Sort alphabetically Sort by EU Contribution Expand all Collapse all CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE France EU contribution No data Address 3, RUE MICHEL-ANGE 75794 PARIS CEDEX 16 See on map Total cost No data TECHNISCHE UNIVERSITEIT DELFT Netherlands EU contribution No data Address JULIANALAAN 134 2628 BL DELFT See on map Total cost No data UNIVERSITY OF LEEDS United Kingdom EU contribution No data Address WOODHOUSE LANE LS2 9JT LEEDS See on map Total cost No data UNIVERSITY OF STRATHCLYDE United Kingdom EU contribution No data Address RICHMOND STREET 16 G1 1XQ GLASGOW See on map Total cost No data
