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Power Optimisation for Embedded SysTems

Ziel

Power dissipation is increasingly becoming a limiting factor in the integration of complex SoC (System-on-Chip) designs. This is starting to impact the mobility of ubiquitous computation and communication and affecting the cost and reliability of communication systems and networks. Power management and reduction is most efficiently achieved at the system level, at the stage when algorithms are developed and partitioning is done. Experiments have shown that power reduction of several orders of magnitude can be achieved by optimisations at this level of abstraction. The POET project drives this opportunity as its main objective: development of methodologies and tools for power estimation and optimisation of combined SW and HW descriptions of SoC. POET targets the algorithmic level for both HW and SW as well as the functional Register Transfer Level of abstraction where power optimisations offer the largest potential.

Objectives:
The main objective of the POET project is to develop a new design methodology and tool suite for power estimation and optimisation in heterogeneous embedded SoC designs. The key innovation of the approach is to enable design space exploration for low power system architectures, algorithm optimisations and system partitioning -- from the earliest design steps seamlessly through to RT level (i.e. to the interface with standard industrial synthesis tools). The POET design framework will operate at each level of abstraction, i.e. algorithmic,hardware/software partition, cycle-accurate RT level. POET tools will manage and optimise all major contributors to power dissipation in large SoC designs such as ASICs, cores and processors, memories, communication and I/O interfaces.

Work description:
The workplan is structured into eight Workpackages (WP): six technical (WP1-6), one commercial(WP7), and one administrative (WP8).

WP1 specifies the design flow for the development of low power integrated SoCs, defining the interfaces between the different power optimisation tools so they are able to interact seamlessly.
WP2 develops methodologies to optimise power consumption of the software components of SoC design -- based on the power estimation techniques previously developed and enhanced in WP5. The SoC design outcome will be dependent on the architecture adopted in terms of processor and memory hierarchy, and on the compilation and operating system environment.
WP3 deals with the development of methodologies and develops a prototype tool for interconnect and data manipulation. WP3 also develops the transfer and storage driven power optimisation of executable specifications of hardware units, including memory structures; these will be implemented using System C and C++.
WP4 deals with the development of methodologies and prototype tools for power optimisation of memory sub-systems, and of the memory-processor and data-path communication interfaces. This enables automatic insertion of power management circuitry in cycle-accurate RT level descriptions, and automated synthesis of power managed RT level library macros.
WP5 enhances the capabilities of power estimation tools already developed by Partners 1, 2 and 3 (partly in a previous ESPRIT project) so that the tools can interact fully with the new optimisation tools developed in WP2, WP3 and WP4.
WP6 deals with the integration of the tools developed in POET, and with industrial evaluation of the tools in the application domains of the user partners.
WP7 deals with both internal and external exploitation and commercialisation.
WP8 deals with project co-ordination and management of POET, including financial and contractual administration.

Milestones:
Milestones and expected results:
Key milestones and results:
-- the preliminary and final versions of the different estimators and optimisers
-- integration of the POET tool chain
-- industrial evaluation of the tools
-- implementation of the exploitation plan

Wissenschaftliches Gebiet (EuroSciVoc)

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KURATORIUM OFFIS E. V.
EU-Beitrag
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Beteiligte (6)

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