Objectif The PLASIC project was concerned with the performance and reliability of plastic-encapsulated CMOS ASICs, and its goal was to develop guidelines on how to build and evaluate reliable plastic packages for VLSI devices for high reliability applications, such as those encountered in telecommunications, industrial control, and automotive and computer electronics.This paper highlights the approach used for the development and evaluation of a low stress high pincount PQFP package for high reliability complementary metal oxide semiconductor application specific integrated circuit applications in the field of telecommunications, industrial control, automotive and computer electronics. Reliable die attach materials and moulding compounds for a low stress PQFP package are selected as a result of intensive material evaluation and process optimization, Mechanical stress simulations have been carried out to explain and confirm the mechanical stress measurements performed with the use of specially designed stress sensitive test devices. Reliability tests based on accelerated testing techniques have been performed using dedicated reliability test devices in order to assess the reliablity performance of the developed PQFP package. The developed package successfully passes highly accelerated stress and temperature cycling tests. The analysis with acoustic scanning microscopy shows that die package separation or delamination mainly occurs at the die corner on a limited number of devices.The PLASIC project is concerned with the performance and reliability of plastic encapsulated complementary metal oxide semiconductor (CMOS) application specific integrated circuits (ASIC) and its goal is to develop guidelines on how to build and evaluate reliable plastic packages for very large scale integration (VLSI) devices for high reliability applications.Packaging materials and processes are being studied and optimized, and the stress quantified. The selection of a low stress die attach material and molding compound has been performed and work on the assembly process has been completed.Device shifts are being investigated and interdependencies between reliability and front end processing analysed, as well as between reliability and design rules.Modelling tools are being developed with the aim of evaluating the thermal and mechanical stress induced on the ASIC devices by both the plastic packaging technology and the surface mounting of the packages on the system boards of end users.2-dimensional plain strain finite element models of PQFP have been developed. Extensive work was carried out on these models to study the influence of complete and partial delamination on the thermomechanical stress distribution within the package.3-dimensional finite element techniques with temperature dependent material properties have been used to investigate the packaging stress on the surface of a die encapsulated in a plastic material.An innovative accelerated humidity test method (HAST) has been evaluated and compared to the conventional one (THB). As a result of this study, a method for fast qualification procedures, based on HAST and temperature cycling, has been issued to replace the existing ones, saving qualification time.Special emphasis was put on the performance and reliability evaluation of complex and advanced plastic-packaged CMOS ASICs, processed using 1.0 micron technologies. Champ scientifique natural scienceschemical sciencesinorganic chemistryinorganic compoundsnatural sciencesphysical sciencesopticsmicroscopynatural sciencesphysical scienceselectromagnetism and electronicssemiconductivityengineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunications Programme(s) FP2-ESPRIT 2 - European strategic programme (EEC) for research and development in information technologies (ESPRIT), 1987-1992 Thème(s) Data not available Appel à propositions Data not available Régime de financement Data not available Coordinateur MIETEC Contribution de l’UE Aucune donnée Adresse WESTERRING, 15 9700 OUDENAARDE Belgique Voir sur la carte Coût total Aucune donnée Participants (5) Trier par ordre alphabétique Trier par contribution de l’UE Tout développer Tout réduire Alcatel SEL AG Allemagne Contribution de l’UE Aucune donnée Adresse Lorenzstraße 10 70435 Stuttgart Voir sur la carte Coût total Aucune donnée ELEKTRONIKCENTRALEN Danemark Contribution de l’UE Aucune donnée Adresse VENLIGHEDSVEJ, 4 2970 HOERSHOLM Voir sur la carte Coût total Aucune donnée NATIONAL MICROELECTRONICS RESEARCH CENTRE Irlande Contribution de l’UE Aucune donnée Adresse PROSPECT ROW CORK Voir sur la carte Coût total Aucune donnée SGS Thomson Microelectronics SA France Contribution de l’UE Aucune donnée Adresse 17 avenue des Martyrs 38340 Grenoble Voir sur la carte Coût total Aucune donnée Thomson Microelectronics Srl (SGS) Italie Contribution de l’UE Aucune donnée Adresse Via Carlo Olivetti 20041 Agrate Brianza Milano Voir sur la carte Coût total Aucune donnée