Design and validation of Ultra-Reprogrammable sOCs

Informazioni relative al progetto

DUROC

ID dell’accordo di sovvenzione: 101004206

DOI

10.3030/101004206

Data della firma CE 27 Ottobre 2020

Data di avvio 1 Marzo 2021

Data di completamento 31 Luglio 2026

Finanziato da

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies – Space

Costo totale

€ 3 210 673,75

Contributo UE

€ 3 047 423,75

Coordinato da

NANOXPLORE
France

Periodic Reporting for period 1 - DUROC (Design and validation of Ultra-Reprogrammable sOCs)

Periodo di rendicontazione: 2021-03-01 al 2022-05-31

Sintesi del contesto e degli obiettivi generali del progetto

The DUROC project sets clear and measurable main objectives to reach a TRL 4 from TRL 2 as follows in 2 years:
• Specifiy and design the next generation of ultra-programmable SoC (ULTRA7) taking benefit of leasson learnt from DAHLIA project (TRL 2)
• Introduce the ARM 73 processor for very high performance processing specificly designed for advanced process node
• Validate the SoC on a rad-hard demonstrator in 7nm FinFET technology from TSMC (TRL 4)
• Validate reliability and radiation hardening performance of 7nm FinFET (TRL 4)
• Propose a strategy and development plan up to flight model for the next ultra-reprogrammable SoC (ULTRA7)
• Define the right approach for future SiP use in space applications
At the end of the project, Europe will have all required technical information to be in a position to develop multiple components (SoC FPGA, ASIC etc) on 7nm FinFET which will be the most advanced process node for space. DUROC will bring Europe to an unprecedented leadership position in VLSI electronic for space.

Lavoro eseguito dall’inizio del progetto fino alla fine del periodo coperto dalla relazione e principali risultati finora ottenuti

WP1: ADS-G had collected from TAS/ADS-F/NX/ESA and CNES SoC requirements. The MPSoC specification has been done. Task 1.3 SiP analysis has started in January 2022 with SIP testing literature review.

WP2: NX has developed a preliminary architecture with the help of ADS-F taking into account the end-users’ requirements. The final architecture has been established.

WP3: Task 3.1 not yet started, NX still in discussion with CNES for the parallel activity that will fund the library hardening. NX has developed a preliminary architecture with the help of ADS-F taking into account the end-users’ requirements. The final architecture has been established. IROC carried out the tasks to get ready the TFIT model associated with the TSMC 7nm FinFET technology

WP4: Not yet started, will start in month 22.

WP5: The Duroc website is online, NX will participate to conferences in 2022. In 2023 more dissemination will done.

Progressi oltre lo stato dell’arte e potenziale impatto previsto (incluso l’impatto socioeconomico e le implicazioni sociali più ampie del progetto fino ad ora)

• Reduce the dependence on critical technologies and capabilities from outside Europe for future space applications by providing an ITAR free advanced rad-hard FPGA
• Develop or regain in the mid-term the European capacity to operate independently in space with access to new generation of rad-hard FPGA beyond current state of the art
• Enhance the technical capabilities and overall competitiveness of European space industry satellite vendors on the worldwide market by giving prime access to exportation restriction free high performance technologies
• Work package dedicated to the development of a commercial evaluation of the technology with a full range of recurring products. The future rad-hard FPGA will be available in space qualified package and commercial package with a clear pricing strategy to maximise product dissemination outside space markets
• Improve the overall European space technology landscape and complement the activities of European and national space programmes. DUROC is clearly set up to complement the ongoing ESA/CNES BRAVE project
• DUROC will have clear social and environmental impacts by offering a very versatile technology able to meet multiple applications in various markets with the same device. It will also facilitate SMEs access to advance space applications

duroc-website.png