Description du projet
Principes de conception modulaire pour des systèmes matériels-logiciels sûrs et sécurisés
De nombreux domaines critiques pour la sécurité de nos vies sont contrôlés par des systèmes informatiques, des commandes d’airbag dans les voitures et des trains d’atterrissage des avions aux infrastructures essentielles telles que l’approvisionnement en énergie et les télécommunications. Cependant, un aspect crucial des systèmes informatiques, l’interface matériel-logiciel, rend impossible le développement d’applications sûres et sécurisées à un niveau fondamental. Cela a été mis en évidence en 2018, lorsque les attaques Spectre et Meltdown ont été décrites pour la première fois. Depuis lors, les développeurs de matériel et de logiciels s’efforcent d’atténuer les vulnérabilités qui en résultent. Le projet SafeSecS, financé par l’UE, relève ce défi avec un nouveau cadre pour garantir les principales fonctionnalités de sûreté et de sécurité au niveau logiciel, en plus de nouveaux contrats matériel-logiciel.
Objectif
Trains, planes, and other safety- and security-critical systems that our society relies on are controlled by computer systems, as is much of our critical infrastructure, including the power grid and cellular networks. But can we trust in the safety and security of these systems?
The starting point of SafeSecS is the observation that today’s hardware-software abstractions, instruction set architectures (ISAs), are fundamentally inadequate for the development of safe or secure systems. Indeed, ISAs abstract from timing, making it impossible to develop safety-critical systems that have to satisfy real-time constraints on top of them. Neither do ISAs provide sufficient security guarantees, making it impossible to develop secure systems on top of them. As a consequence, engineers are forced to rely on brittle timing and security models that are proven wrong time and again, as evidenced e.g. by the recent Spectre attacks; putting our society at risk.
SafeSecS will attack the problem at its root by introducing a framework centered around hardware-software contracts that extend the guarantees provided by ISAs to capture key non-functional properties. Hardware-software contracts formally capture the expectations on correct hardware implementations and they lay the foundation for achieving safety and security guarantees as the software level. Below the hardware-software interface, SafeSecS will contribute modular design principles and tools to construct microarchitectures that provably satisfy a given hardware-software contract. Above the hardware-software interface, SafeSecS will develop rigorous, precise, and scalable techniques to guarantee key safety and security properties at the software level on top of hardware-software contracts. As a whole, SafeSecS will enable the systematic engineering of safe and secure hardware-software systems we can trust in.
Champ scientifique
- natural sciencescomputer and information sciencessoftware
- engineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineering
- natural sciencescomputer and information sciencescomputer securitymalicious software
- natural sciencescomputer and information sciencescomputer securitydata protection
- natural sciencescomputer and information sciencescomputer securitynetwork security
Programme(s)
Thème(s)
Régime de financement
ERC-ADG - Advanced GrantInstitution d’accueil
66123 Saarbrucken
Allemagne